Verilog design of bist on AES256 processor core with FPGA implementation

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Title:

Verilog design of bist on AES256 processor core with FPGA implementation

Personal Author:

Hew, Kean Yung, 1981-

Publication Information:

2008

Physical Description:

xv, 90 p. : ill. ; 30 cm.

General Note:

Supervisor : Prof. Dr. Mohamed Khalil Mohd. Hani

Also available in compact disc version : CP 018234 ra

Subject Term:

Verilog (Computer hardware description language)

Field programmable gate arrays

Added Author:

Mohamed Khalil Mohd. Hani,

Added Corporate Author:

Fakulti Kejuruteraan Elektrik

DSP_DISSERTATION:

Thesis ( Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik )) - Universiti Teknologi Malaysia, 2008

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... FKE Library	FKE30000002741	TK7885.7 H48 2008 raf	Closed Access Thesis	UTM Master Thesis (Closed Access)	Searching... Unknown
Searching... Perpustakaan Raja Zarith Sofiah	30000010143453	TK7885.7 H48 2008 raf	Closed Access Thesis	UTM Master Thesis (Closed Access)	Searching... Unknown

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