The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL

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2008

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xiv, 77 p. : ill. ; 30 cm.

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Also available in CD-ROM : CP 017450 ra

Supervisor : Prof. Dr Mohamed Khalil Mohd. Hani

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Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Universit Teknologi Malaysia, 2008

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... FKE Library	FKE30000002738	QA76.5 L55 2008 raf	Closed Access Thesis	UTM Master Thesis (Closed Access)	Searching... Unknown
Searching... Perpustakaan Raja Zarith Sofiah	30000010143497	QA76.5 L55 2008 raf	Closed Access Thesis	UTM Master Thesis (Closed Access)	Searching... Unknown