Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR)

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Title:

Design for testability (DFT) method at register transfer level design for greatest common divisor (GCD) and finite impulse response (FIR)

Personal Author:

Tim, Wei Lun, 1992-, author

Publication Information:

2016

Physical Description:

1 CD-ROM ; 12 cm.

General Note:

Also available in printed version : TK7868.L6 T56 2016 raf

Supervisor : Dr. Norlina Paraman

Subject Term:

Combinational circuits

Added Author:

Norlina Paraman,

Added Corporate Author:

Fakulti Kejuruteraan Elektrik

DSP_DISSERTATION:

Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2016

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010352350	CP 061502 ra	UTM Special Collection - Computer File	Compact Disc Accompanies UTM Thesis/Project Paper	Searching... Unknown

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