Title:
Digital systems design using VHDL
Personal Author:
Edition:
2nd ed.
Publication Information:
Mason, OH : Thomson, 2008
Physical Description:
1 CD-ROM ; 12 cm.
ISBN:
9780534384623
9780495244707
General Note:
Accompanies text of the same title : TK7888.4 R674 2008
Available:*
Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
|---|---|---|---|---|---|
Searching... | 30000010194432 | CP 12169 | Computer File Accompanies Open Access Book | Compact Disc Accompanies Open Access Book | Searching... |
Searching... | 30000010278859 | CP 12169 | Computer File Accompanies Open Access Book | Compact Disc Accompanies Open Access Book | Searching... |
Searching... | 30000003485632 | CP 12169 | Computer File Accompanies Open Access Book | Compact Disc Accompanies Open Access Book | Searching... |
Searching... | 30000003500190 | CP 12169 | Computer File Accompanies Open Access Book | Compact Disc Accompanies Open Access Book | Searching... |
On Order
Summary
Summary
Written for an advanced-level course in digital systems design, DIGITAL SYSTEMS DESIGN USING VHDL integrates the use of the industry-standard hardware description language VHDL into the digital design process. Following a review of basic concepts of logic design, the author introduces the basics of VHDL, and then incorporates more coverage of advanced VHDL topics. Rather than simply teach VHDL as a programming language, this book emphasizes the practical use of VHDL in the digital design process.
Table of Contents
| Preface |
| 1 Review Of Logic Design Fundamentals |
| Combinational Logic |
| Boolean Algebra and Algebraic Simplification |
| Karnaugh Maps |
| Designing with NAND and NOR Gates |
| Hazards in Combinational Networks |
| Flip-flops and Latches |
| Meanly Sequential Network Design |
| Design of a Moore Sequential Network |
| Equivalent States and Reduction of State Tables |
| Sequential Network Timing |
| Setup and Hold Times |
| Synchronous Design |
| Tristate Logic and Busses |
| 2 Introduction To Vhdl Vhdl |
| Description of Combinational Networks |
| Modeling Flip-flops using VHDL Processes |
| VHDL Models for a Multiplexer |
| Compilation and Simulation of VHDL Code |
| Modeling a Sequential Machine |
| Variables, Signals, and Constants |
| Arrays |
| VHDL Operators |
| VHDL Functions |
| VHDL Procedures |
| Packages and Libraries |
| VHDL Model for a 74163 Counter |
| 3 Designing With Programmable Logic Devices |
| Read-only Memories |
| Programmable Logic Arrays (PLAs) |
| Programmable Array Logic (PALs) |
| Other Sequential Programmable Logic Devices (PLDs) |
| Design of a Keypad Scanner |
| 4 Design Of Networks For Arithmetic Operations |
| Design of a Serial Adder with Accumulator |
| State Graphs for Control Networks |
| Design of a Binary Multiplier |
| Multiplication of Signed Binary Numbers |
| Design of a Binary Divider |
| 5 Digital Design With Sm Charts |
| State Machine Charts |
| Derivation of SM Charts |
| Realization of SM Charts |
| Implementation of the Dice Game |
| Alternative Realizations for SM Charts Using Microprogramming |
| Linked State Machines |
| 6 Designing with programmable gate arrays and complex programmable logic devices XILINX 3000 Series FPGAs |
| Designing with FPGAs |
| XILINX 4000 Series FPGAs |
| Using a One-Hot State Assignment |
| Altera Complex Programmable Logic Devices (CPLDs) |
| Altera FLEX 10K Series CPLDs |
| 7 Floating-Point Arithmetic |
| Representation of Floating-Point Numbers |
| Floating-Point Multiplication |
| Other Floating-Point Operations |
| 8 Additional Topics In VHDL Attributes |
| Transport and Inertial Delays |
| Operator Overloading |
| Multivalued Logic and Signal Resolution |
| IEEE-1164 Standard Logic |
| Generics |
| Generate Statements |
| Synthesis of VHDL Code |
| Synthesis Examples |
| Files and TEXTIO |
| 9 VHDL Models For Memories And Busses |
| Static RAM Memory |
| A Simplified 486 Bus Model |
| Interfacing Memory to a Microprocessor Bus |
| 10 Hardware Testing And Design For Testability |
| Testing Combinational Logic |
| Testing Sequential Logic |
| Scan Testing |
| Boundary Scan |
| Built-In Self-Test |
| 11 Design Examples Uart |
| Design |
| Description of the MC68HC05 Microcontroller |
| Design of Microcontroller CPU |
| Completion of the Microcontroller Design |
| Appendix A Vhdl Language Summary |
| Appendix B Bit Package |
| Appendix C Textio Package |
| Appendix D Behavioral Vhdl Code For M6805 CPU |
| Appendix E M6805 CPU Vhdl Code For Synthesis |
| Appendix F Projects |
| References |
| Index |
