Designing SOCs with configured cores : unleashing the Tensilica Xtensa and diamond cores

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Title:

Personal Author:

Leibson, Steve

Series:

The Morgan Kaufmann series in systems on silicon

Publication Information:

Amsterdam : Morgan Kaufmann Publishers, 2006

ISBN:

9780123724984

Subject Term:

Embedded computer systems -- Design and construction

Systems on a chip -- Design and construction

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010141296	TK7895.E42 L44 2006	Open Access Book	Book	Searching... Unknown

Microprocessor cores used for SOC design are the direct descendents of Intel's original 4004 microprocessor. Just as packaged microprocessor ICs vary widely in their attributes, so do microprocessors packaged as IP cores. However, SOC designers still compare and select processor cores the way they previously compared and selected packaged microprocessor ICs. The big problem with this selection method is that it assumes that the laws of the microprocessor universe have remained unchanged for decades. This assumption is no longer valid.

Processor cores for SOC designs can be far more plastic than microprocessor ICs for board-level system designs. Shaping these cores for specific applications produces much better processor efficiency and much lower system clock rates. Together, Tensilica's Xtensa and Diamond processor cores constitute a family of software-compatible microprocessors covering an extremely wide performance range from simple control processors, to DSPs, to 3-way superscalar processors. Yet all of these processors use the same software-development tools so that programmers familiar with one processor in the family can easily switch to another.

This book emphasizes a processor-centric MPSOC (multiple-processor SOC) design style shaped by the realities of the 21st-century and nanometer silicon. It advocates the assignment of tasks to firmware-controlled processors whenever possible to maximize SOC flexibility, cut power dissipation, reduce the size and number of hand-built logic blocks, shrink the associated verification effort, and minimize the overall design risk.

Foreword	p. xiii
Preface	p. xv
Acknowledgements	p. xix
1 Introduction to 21st-Century SOC Design	p. 1
1.1 The Start of Something Big	p. 1
1.2 Few Pins = Massive Multiplexing	p. 4
1.3 Third Time's a Charm	p. 6
1.4 The Microprocessor: A Universal System Building Block	p. 6
1.5 The Consequences of Performance-in the Macro World	p. 10
1.6 Increasing Processor Performance in the Micro World	p. 12
1.7 I/O Bandwidth and Processor Core Clock Rate	p. 13
1.8 Multitasking and Processor Core Clock Rate	p. 14
1.9 System-Design Evolution	p. 15
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches	p. 20
1.11 The Rise of MPSOC Design	p. 24
1.12 Veering Away from Processor Multitasking in SOC Design	p. 26
1.13 Processors: The Original, Reusable Design Block	p. 26
1.14 A Closer Look at 21st-Century Processor Cores for SOC Design	p. 28
Bibliography	p. 31
2 The SOC Design Flow	p. 33
2.1 System-Design Goals	p. 33
2.2 The ASIC Design Flow	p. 34
2.3 The ad-hoc SOC Design Flow	p. 38
2.4 A Systematic MPSOC Design Flow	p. 45
2.5 Computational Alternatives	p. 47
2.6 Communication Alternatives	p. 48
2.7 Cycle-Accurate System Simulation	p. 50
2.8 Detailed Implementation	p. 51
2.9 Summary: Handling SOC Complexity	p. 53
Bibliography	p. 54
3 Xtensa Architectural Basics	p. 55
3.1 Introduction to Configurable Processor Architectures	p. 56
3.2 Xtensa Registers	p. 58
3.3 Register Windowing	p. 58
3.4 The Xtensa Program Counter	p. 60
3.5 Memory Address Space	p. 61
3.6 Bit and Byte Ordering	p. 61
3.7 Base Xtensa Instructions	p. 65
3.8 Benchmarking the Xtensa Core ISA	p. 69
Bibliography	p. 74
4 Basic Processor Configurability	p. 75
4.1 Processor Generation	p. 75
4.2 Xtensa Processor Block Diagram	p. 79
4.3 Pre-Configured Processor Cores	p. 80
4.4 Basics of TIE	p. 80
4.5 TIE Instructions	p. 81
4.6 Improving Application Performance Using TIE	p. 84
4.7 TIE Registers and Register Files	p. 90
4.8 TIE Ports	p. 91
4.9 TIE Queue Interfaces	p. 92
4.10 Combining Instruction Extensions with Queues	p. 95
4.11 Diamond Standard Series Processor Cores-Dealing with Complexity	p. 96
Bibliography	p. 98
5 MPSOC System Architectures and Design Tools	p. 99
5.1 SOC Architectural Evolution	p. 100
5.2 The Consequences of Architectural Evolution	p. 103
5.3 Memory Interfaces	p. 104
5.4 Memory Caches	p. 105
5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF	p. 106
5.6 The PIF	p. 106
5.7 Ports and Queue Interfaces	p. 107
5.8 SOC Connection Topologies	p. 108
5.9 Shared-Memory Topologies	p. 108
5.10 Direct Port-Connected Topologies	p. 110
5.11 Queue-Based System Topologies	p. 114
5.12 Existing Design Tools for Complex SOC Designs	p. 115
5.13 MPSOC Architectural-Design Tools	p. 119
5.14 Platform Design	p. 121
5.15 An MPSOC-Design Tool	p. 122
5.16 MPSOC System-Level Simulation Example	p. 126
5.17 SOC Design in the 21st Century	p. 128
Bibliography	p. 128
6 Introduction to Diamond Standard Series Processor Cores	p. 131
6.1 The Diamond Standard Series of 32-bit Processor Cores	p. 131
6.2 Diamond Standard Series Software-Development Tools	p. 133
6.3 Diamond Standard Series Feature Summary	p. 134
6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison	p. 135
6.5 Diamond-Core Local-Memory Interfaces	p. 137
6.6 The PIF Main Bus	p. 139
6.7 Diamond-Core Ports and Queues	p. 139
6.8 Diamond Standard Series Core Instructions	p. 144
6.9 Zero-Overhead Loop Instructions	p. 144
6.10 Miscellaneous Instructions	p. 145
6.11 Synchronization Instructions	p. 146
6.12 16-bit Multiply and Multiply/Accumulate Instructions	p. 146
6.13 32-bit Multiply Instructions	p. 147
6.14 Diamond-Development Tools	p. 148
6.15 Other Specialized Diamond Standard Series Processor Instructions	p. 148
6.16 Choosing a Diamond	p. 149
Bibliography	p. 150
7 The Diamond Standard Series 108Mini Processor Core	p. 151
7.1 The Configurable Processor as Controller	p. 153
7.2 Diamond 108Mini Processor Core Interfaces	p. 153
7.3 The Diamond RPU	p. 155
7.4 Direct Input and Output Ports	p. 157
7.5 System Design with Diamond 108Mini Processor Cores	p. 160
7.6 Low-Power System Design and Operation	p. 164
Bibliography	p. 166
8 The Diamond 212GP Controller Core	p. 167
8.1 A General-Purpose Processor Core	p. 168
8.2 Diamond 212GP Controller Core Interfaces	p. 168
8.3 The XLMI Port	p. 168
8.4 The Diamond 212GP Processor Memory Map	p. 171
8.5 The 212GP RPU	p. 174
8.6 Direct Input and Output Ports	p. 176
8.7 The Diamond 212GP Controller's Cache Interfaces	p. 177
8.8 System Design with the Diamond 212GP Processor Core	p. 179
Bibliography	p. 182
9 The Diamond 232L CPU Core	p. 183
9.1 The Diamond 232L: A Full-Featured CPU Core	p. 184
9.2 Diamond 232L CPU Core Interfaces	p. 184
9.3 The Diamond 232L CPU Memory Map	p. 184
9.4 The Diamond 232L Cache Interfaces	p. 188
9.5 The Diamond 232L MMU	p. 188
9.6 Privilege Levels and Rings	p. 193
9.7 System Design with the Diamond 232L CPU Core	p. 195
Bibliography	p. 198
10 The Diamond 570T Superscalar CPU Core	p. 199
10.1 The Diamond 570T: A High-Performance CPU Core	p. 202
10.2 Diamond 570T CPU Core Interfaces	p. 204
10.3 The Diamond 570T CPU Memory Map	p. 204
10.4 The Diamond 570T CPU's Cache Interfaces	p. 206
10.5 The Diamond 570T CPU's RPU	p. 209
10.6 Direct Input and Output Ports	p. 209
10.7 Input and Output Queue Interfaces	p. 212
10.8 System Design with the Diamond 570T CPU Core	p. 214
Bibliography	p. 216
11 The Diamond 330HiFi audio DSP Core	p. 219
11.1 300 Instructions Boost Audio Performance	p. 219
11.2 The Diamond 330HiFi: A High-Performance audio DSP Core	p. 223
11.3 Diamond 330HiFi audio DSP Core Interfaces	p. 223
11.4 The Diamond 330HiFi audio DSP Core's Memory Map	p. 223
11.5 The Diamond 330HiFi audio DSP Core's Cache Interfaces	p. 227
11.6 The Diamond 330HiFi audio DSP Core's Region-Protection Unit	p. 229
11.7 Input- and Output-Queue Interfaces	p. 229
11.8 System Design with the Diamond 330HiFi audio DSP Core	p. 233
Bibliography	p. 234
12 The Diamond 545CK DSP Core	p. 235
12.1 The Diamond 545CK DSP Core's Instruction Format	p. 235
12.2 A High-Performance DSP Core	p. 238
12.3 Diamond 545CK DSP Core Interfaces	p. 240
12.4 The Diamond 545CK DSP Core's Memory Map	p. 241
12.5 The Diamond 545CK DSP Core's Region-Protection Unit	p. 243
12.6 Input- and Output-Queue Interfaces	p. 244
12.7 System Design with the Diamond 545CK DSP Core	p. 247
Bibliography	p. 247
13 Using Fixed Processor Cores in SOC Designs	p. 249
13.1 Toward a 21st-Century SOC Design Strategy	p. 249
13.2 The ITRS Proposal for SOC Design	p. 252
13.3 On-Chip Communications for SOCs	p. 257
13.4 NoC	p. 259
13.5 The Three NoC Temptations	p. 262
13.6 GALS On-Chip Networks	p. 266
13.7 Software Considerations for MPSOCs	p. 266
Bibliography	p. 270
14 Beyond Fixed Cores	p. 271
14.1 A Viable Alternative to Manual RTL Design and Verification	p. 271
14.2 The Conventional, Embedded Software-Development Flow	p. 272
14.3 Fit the Processor to the Algorithm	p. 274
14.4 Accelerating the Fast Fourier Transform	p. 274
14.5 Accelerating an MPEG-4 Decoder	p. 276
14.6 Boost Throughput with Multiple Operations per Cycle	p. 279
14.7 High-Speed I/O for Processor-Based Function Blocks	p. 281
14.8 The Single-Bus Bottleneck	p. 282
14.9 Alone, Faster is Not Necessarily Better	p. 285
Bibliography	p. 289
15 The Future of SOC Design	p. 291
15.1 Grand Challenges and Disaster Scenarios	p. 291
15.1.1 SOC Disaster Scenario 1: Insufficient Productivity	p. 293
15.1.2 SOC Disaster Scenario 2: Excessive System Power Dissipation	p. 294
15.1.3 SOC Disaster Scenario 3: Loss of Manufacturability	p. 295
15.1.4 SOC Disaster Scenario 4: Excessive Signal Interference	p. 296
15.1.5 SOC Disaster Scenario 5: Deteriorating Chip Reliability	p. 296
15.2 Avoiding the SOC Disaster Scenarios	p. 296
15.2.1 Avoiding Disaster Scenario 1: Insufficient Productivity	p. 297
15.2.2 Avoiding Disaster Scenario 2: Excessive System Power Dissipation	p. 298
15.2.3 Avoiding Disaster Scenario 3: Loss of Manufacturability	p. 299
15.2.4 Avoiding Disaster Scenario 4: Excessive Signal Interference	p. 300
15.2.5 Avoiding Disaster Scenario 5: Deteriorating Chip Reliability	p. 301
15.3 System-Level Design Challenges	p. 301
15.4 The Future Direction of SOC Design	p. 304
15.5 Systolic Processing	p. 305
15.6 Cluster Computing and NoCs	p. 309
15.7 The Research Accelerator for Multiple Processors Project	p. 309
15.8 21st-Century SOC Design	p. 311
Bibliography	p. 312
Index	p. 315

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