Error control coding for B3G/4G wireless systems : paving the way to IMT-advanced standards

Covering the fast evolving area of advanced coding, Error Control Coding for B3G/4G Wireless Systems targets IMT-Advanced systems to present the latest findings and implementation solutions. The book begins by detailing the fundamentals of advanced coding techniques such as Coding, Decoding, Design, and Optimization. It provides not only state-of-the-art research findings in 3D Turbo-codes, non-binary LDPC Codes, Fountain, and Raptor codes, but also insights into their real-world implementation by examining hardware architecture solutions, for example VLSI complexity, FPGA, and ASIC. Furthermore, special attention is paid to Incremental redundancy techniques, which constitute a key feature of Wireless Systems.

A promising application of these advanced coding techniques, the Turbo-principle (also known as iterative processing), is illustrated through an in-depth discussion of Turbo-MIMO, Turbo-Equalization, and Turbo-Interleaving techniques. Finally, the book presents the status of major standardization activities currently implementing such techniques, with special interest in 3GPP UMTS, LTE, WiMAX, IEEE 802.11n, DVB-RCS, DVB-S2, and IEEE 802.22. As a result, the book coherently brings together academic and industry vision by providing readers with a uniquely comprehensive view of the whole topic, whilst also giving an understanding of leading-edge techniques.

Includes detailed coverage of coding, decoding, design, and optimization approaches for advanced codes Provides up to date research findings from both highly reputed academics and industry standpoints Presents the latest status of standardization activities for Wireless Systems related to advanced coding Describes real-world implementation aspects by giving insights into architecture solutions for both LDPC and Turbo-codes Examines the most advanced and promising concepts of turbo-processing applications: Turbo-MIMO, Turbo-Equalization, Turbo-Interleaving

Author Notes

Thierry Lestable received his Engg. Degree and Ph.D from the Ecole Supérieure d'Electricité (Supelec) in 1997 and 2003 respectively. He has more than 12 years experience in leading edge Wireless Telecommunications, is author of 40+ international publications, including 2 Wiley Books, and 25+ patents. Since 2008, Dr. Lestable has been Technology & Innovation Manager at SAGEMCOM (Paris, France), in charge of Technology Strategy and Roadmap within CTO office.

Dr. Lestable is expert for the European Commission (FP7), and Eureka Cluster CELTIC, whilst chairing the Machine-to-Machine (M2M) Expert Group in eMobility European Technology Platform. He is the Project Manager of FP7-BeFEMTO project targeting next generation LTE-based Femtocells, and initiated the FP7-EXALTED project dedicated to LTE-based M2M communications. Since 2010, he has been a member of the Telecom Steering Board from System@tic Competitiveness Cluster in France.

Within Alcatel labs (1998-2003), he investigated Multi-Carrier Wireless Systems paving the way for 4G Chinese systems with FuTURE 863 projects. Then, from 2004, Dr. Lestable was with Samsung Electronics Research Institute (SERI), UK, heading the Advanced Technology Group focusing on Advanced Channel Coding (LDPC), Iterative processing and Cross-Layer for MIMO-OFDM based systems. He actively contributed to IEEE 802.16m, and 802.20 standards, whilst participating in European research projects (FP6-WINNER), and creating FP7-DAVINCI Consortium.

Moshe Ran holds a PhD from Tel Aviv University, and has been the head of research and development authority at Holon Institute of Technology (HIT) since 2009. He has 25 years experience in state of the art communications systems and has lead R&D groups in several communication topics including: broadband access technologies, 3G and 4G systems, Short-range communications with focus on Ultra-wideband (UWB) technologies, error correction codes.

Dr. Ran formerly held prominent management and technical positions including CEO of MostlyTek Ltd. He has been an active member in standards bodies and technology-related partnerships including: IEEE802.16, ETSI/BRAN and WWRF. He was the project manager and coordinator of IST-FP6 STREP project named UROOF, targeting UWB over optical fibre for next generation broadband communications. He is a senior member of IEEE and has published more than 60 technical international publications and papers in the areas of error control coding and broadband wireless/wireline integration.

Gerhard Bauch and Claude Berrou and David Declercq and Alexandre Graell I Amat and Youssouf Ould-Cheikh-Mouhamedou and Yannick Saouter and Jossy Sayir and Marcos B.S. TavaresMoshe Ran and Carlos De Segovia and Omer RanStefania Sesia and Charly PoulliatFrank KienleIsabelle Siaud and Ming Jiang and Anne-Marie Ulmer-Moll and Maryline Hélard and Thierry Lestable and Carlos De SegoviaMarie-Hélene Hamon and Thierry Lestable and Isabelle Siaud)

About the Editors	p. xi
Contributors	p. xiii
Preface	p. xv
Acknowledgments	p. xvii
Abbreviations	p. xix
1 Coding	p. 1
1.1 General Code Types	p. 1
1.2 Designing Codes Based on Graphs	p. 7
1.3 Pseudorandom Designs	p. 8
1.3.1 Pseudorandom Designs for Turbo Codes	p. 8
1.3.2 Structured Designs	p. 14
1.3.3 Code Optimization	p. 22
1.4 Repeat Accumulate Codes	p. 25
1.5 Binary versus Nonbinary	p. 28
1.6 Performance Results of Nonbinary LDPC Codes	p. 30
1.6.1 Small Codeword Lengths	p. 30
1.6.2 High-Order Modulations	p. 31
1.6.3 Brief Presentation of NB-LDPC Decoders	p. 33
1.7 Three-Dimensional (3D) Turbo Codes	p. 34
1.7.1 The Encoding Structure	p. 35
1.7.2 Code Optimization	p. 37
1.7.3tDecoding the 3D Turbo Code p. 42
1.7.4 Simulation Results	p. 43
1.8 Conclusions	p. 45
References	p. 46
2 Decoding	p. 49
2.1 Algebraic Soft-Decision (ASD) and Reliability-Based Decoders	p. 50
2.1.1 Reliability-Based Soft-Decision Decoding	p. 51
2.1.2 Adaptive Iterative Soft-Decision Decoders for Short Packet Lengths	p. 54
2.1.3 Algebraic Soft-Decision and Reed-Solomon Codes	p. 61
2.2 Graph versus Trellis Decoding Algorithms	p. 63
2.2.1 BP-Based Algorithms
2.2.2 BCJR-Based Algorithms	p. 64
References	p. 65
3 Incremental Redundancy for Coding	p. 69
3.1 Introduction	p. 69
3.2 Retransmission Protocols (ARQ)	p. 70
3.2.1 Stop-and-Wait ARQ Protocol	p. 70
3.2.2 Go-Back-N ARQ Protocol	p. 73
3.2.3 Selective Repeat (SR) ARQ Protocol	p. 74
3.2.4 Summary, and Challenges	p. 75
3.3 HARQ Schemes	p. 76
3.3.1 Type I HARQ	p. 76
3.3.2 Type II HARQ	p. 78
3.3.3 Comparison in Terms of Buffer Requirements	p. 80
3.4 Design of Hybrid ARQ Type II	p. 81
3.4.1 Mathematical System Model	p. 81
3.4.2 Throughput Analysis	p. 83
3 5 Code Design	p. 86
3.5.1 Rate-Compatible Punctured (RCP) Convolutional Codes	p. 88
3.5.2 Rate-Compatible Punctured Turbo Codes	p. 89
3.5.3 Fountain and Raptor Codes	p. 90
3 5.4 Low-Density Parity-Check Codes	p. 96
3.6 Generalization of the Mutual Information Evolution for Incremental Redundancy Protocols	p. 99
3.6.1 Complexity for Iterative Decoding Schemes in the Context of Incremental Redundancy Protocols	p. 101
3.7 ARQ/HARQ in the Standards	p. 102
3.7.7 Retransmission Protocols in 3GPP Standard	p. 103
3.7.2 Retransmission Protocols in Non-3GPP Standard	p. 106
3.8 Conclusions	p. 107
References	p. 107
4 Architecture and Hardware Requirements	p. 113
4.1 Turbo Decoder Implementation	p. 113
4.1.1 Interleaver and Deinterleaver	p. 114
4.1.2 Serial Turbo Decoding	p. 115
4.1.3 Parallel and Shuffled Turbo Decoding	p. 117
4.1.4 Turbo Decoding with Parallel Component Decoder	p. 117
4.1.5 MAP Decoder	p. 119
4.1.6 Branch Metric Calculation	p. 124
4.1.7 State and Path Metrics	p. 127
4.1.8 Duobinary Codes	p. 137
4.1.9 Quantization	p. 139
4.1.10 Normalization	p. 141
4.1.11 Implementation Results	p. 145
4.2 LDPC Decoder Architectures	p. 146
4.2.1 Generic Architecture Template	p. 146
4.2.2 Two-Phase Architecture	p. 149
4.2.3 Two-Phase Architecture with PN Branch	p. 151
4.2.4 Single-Phase Architecture	p. 151
4.2.5 Layered Architecture	p. 153
4.2.6 Other Architecture Concepts	p. 154
4.2.7 Considering Throughput and Latency	p. 155
4.2.8 Considering VLSI Complexity	p. 159
4.2.9 Considering Communications Performance	p. 160
4.2.10 The LDPC Code Decoder Design Space	p. 161
4.2.11 Architecture Parallelism	p. 167
4.2.12 Traveling the Design Space	p. 169
4.2.13 Implementation Issues	p. 170
4.2.14 FPGA Implementation	p. 172
4.2.15 ASIC Implementation	p. 172
4.2.16 Power and Energy Issues	p. 173
4.2.17 Design Studies	p. 177
References	p. 185
5 Turbo-Principle Extensions	p. 189
5.1 Introduction	p. 189
5.2 From Turbo Code to Advanced Iterative Receivers	p. 191
5.2.1 From Turbo Code to Turbo Equalization	p. 191
5.2.2 Turbo-Equalization Principle	p. 194
5.2.3 Turbo Equalization Applied to Iterative Receiver	p. 196
5.3 Turbo-Based Interleaving Techniques	p. 197
5.3.1 General Principles of the Algorithm	p. 199
5.3.2 Mathematical Description	p. 205
5.3.3 Performance as Inner Interleaving to Turbo-FEC Structure	p. 207
5.3.4 Performance as Outer Binary Interleaving	p. 210
5.5.5 Performance as Dynamic Subcarrier Mapping Allocation	p. 214
5.4 Turbo-MIMO Techniques	p. 218
5.4.7 Introduction	p. 218
5.4.2 System Overview	p. 219
5.4.3 Genetically Inspired Optimization	p. 220
5.4.4 Turbo MIMO-OFDM Receiver using GA-Aided Iterative Channel Estimation	p. 222
5.4.5 Simulation Results	p. 225
5.5 Conclusions	p. 236
References	p. 237
6 Standardization	p. 241
6.1 3GPP Systems: UMTS and LTE	p. 241
6.2 IEEE 802.16/WiMAX	p. 242
6.3 IEEE802.11n	p. 245
6.4 Satellite (DVB-RCS, DVB-S2)	p. 246
6.5 Wireless Rural Area Network: The IEEE802.22 standard [IEEE802_22]	p. 248
6.5.1 FEC Coding	p. 250
6.5.2 Outing Interleaving	p. 252
6.6 Others	p. 254
References	p. 254
Index	p. 257

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Table of Contents