Cover image for An enhanced low latency network-on-chip router optimized for prototyping on field programmable gate array
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An enhanced low latency network-on-chip router optimized for prototyping on field programmable gate array
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Thesis (Ph.D (Kejuruteraan Elektrik)) - University Teknologi Malaysia, 2016

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32030000001695 XX(864986.1) Closed Access Thesis UTM PhD Thesis (Open Shelves)
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35000000026272 XX(864986.1) Closed Access Thesis UTM PhD Thesis (Closed Access)
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36000000002381 XX(864986.1) Closed Access Thesis UTM PhD Thesis (Closed Access)
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