FPGA design using verilog - HDL of A 16 bit risc processor

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Title:

FPGA design using verilog - HDL of A 16 bit risc processor

Personal Author:

John, Ang @ Ang, Giap Yeow

Publication Information:

2005

Physical Description:

xvii, 120 p. : ill. ; 30 cm.

General Note:

Supervisor : Prof. Dr. Mohamed Khalil Hj. Mohd. Hani

Subject Term:

Field programmable gate arrays

Motherboards (Microcomputers)

Added Author:

Mohamed Khalil Mohd. Hani

Added Corporate Author:

Fakulti Kejuruteraan Elektrik

DSP_DISSERTATION:

Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2005

Available:*

Library	Item Barcode	[[missing key: search.ChildField.CALLNUMBER]]	Material Type	Item Category 1	Status
Searching... FKE Library	FKE30000001667		Closed Access Thesis	UTM Project Paper (Closed Access)	Searching... Unknown
Searching... Perpustakaan Raja Zarith Sofiah	30000010096294	TK7895.G36 J63 2005 raf	Closed Access Thesis	UTM Project Paper (Closed Access)	Searching... Unknown

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