Cover image for Rapid prototyping of digital systems : a tutorial approach
Title:
Rapid prototyping of digital systems : a tutorial approach
Personal Author:
Edition:
2nd ed.
Publication Information:
Boston : Kluwer Academic Publishers, c2001.
Physical Description:
xiv, 270 p. : ill. ; 26 cm.
ISBN:
9780792374398
General Note:
Includes index.
Added Author:

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30000010239444 TK7895 .G36 H36 2001 Open Access Book Book
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Summary

Summary

Rapid Prototyping of Digital Systems, Second Edition provides an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic.
Design engineers working in industry will also want to consider this book for a rapid introduction to FPLD technology and logic synthesis using commercial CAD tools, especially if they have not had previous experience with the new and rapidly evolving technology.
Two tutorials on the Altera CAD tool environment, an overview of programmable logic, and a design library with several easy-to-use input and output functions were developed for this book to help the reader get started quickly. Early design examples use schematic capture and library components. VHDL is used for more complex designs after a short introduction to VHDL-based synthesis.
A coupon is included with the text for purchase of the new UP 1X board. The additional logic and memory in the UP 1X's FLEX 10K70 is useful on larger design projects such as computers and video games.
The second edition includes an update chapter on programmable logic, new robot sensors and projects, optional Verilog examples, and a meta assembler which can be used to develop assemble language programs for the computer designs in Chapters 8 and 13.


Table of Contents

1 Tutorial I: The 15 Minute Designp. 2
1.1 Design Entry using the Graphic Editorp. 6
1.2 Compiling the Designp. 9
1.3 Simulation of the Designp. 10
1.4 Downloading Your Design to the UP 1 or UP 1X Boardp. 12
1.5 The 10 Minute VHDL Entry Tutorialp. 14
1.6 Compiling the VHDL Designp. 17
1.7 The 10 Minute Verilog Entry Tutorialp. 17
1.8 Compiling the Verilog Designp. 21
1.9 Timing Analysisp. 22
1.10 The Floorplan Editorp. 23
1.11 Symbols and Hierarchyp. 24
1.12 Functional Simulationp. 24
1.13 For additional informationp. 25
1.14 Laboratory Exercisesp. 25
2 The Altera UP 1 and UP 1X CPLD Boardsp. 30
2.1 Programming Jumpersp. 31
2.2 MAX 7000 Device and UP 1 I/O Featuresp. 31
2.3 MAX and FLEX Seven-segment LED Displaysp. 31
2.4 FLEX 10K Device and UP 1 I/O Featuresp. 34
2.5 Obtaining a UP 1 or UP 1X Board and Power Supplyp. 36
3 Programmable Logic Technologyp. 38
3.1 CPLDs and FPGAsp. 41
3.2 Altera MAX 7000S Architecture--A Product Term CPLD Devicep. 42
3.3 Altera FLEX 10K Architecture--A Look-Up Table CPLD Devicep. 43
3.4 Xilinx 4000 Architecture--A Look-Up Table FPGA Devicep. 47
3.5 Computer Aided Design Tools for Programmable Logicp. 49
3.6 Next Generation FPLD CAD toolsp. 50
3.7 Applications of FPLDsp. 50
3.8 Features of New Generation FPLDsp. 50
3.9 For additional informationp. 51
3.10 Laboratory Exercisesp. 52
4 Tutorial II: Sequential Design and Hierarchyp. 54
4.1 Install the Tutorial Files and UP1core Libraryp. 54
4.2 Open the tutor2 Schematicp. 54
4.3 Browse the Hierarchyp. 56
4.4 Using Buses in a Schematicp. 57
4.5 Testing the Pushbutton Counter and Displaysp. 58
4.6 Testing the Initial Design on the UP 1 Boardp. 59
4.7 Fixing the Switch Contact Bounce Problemp. 60
4.8 Testing the Modified Design on the UP 1 Boardp. 61
4.9 Laboratory Exercisesp. 61
5 UP1core Library Functionsp. 66
5.1 UP1core DEC_7SEG: Hex to Seven-segment Decoderp. 67
5.2 UP1core Debounce: Pushbutton Debouncep. 68
5.3 UP1core OnePulse: Pushbutton Single Pulsep. 69
5.4 UP1core Clk_Div: Clock Dividerp. 70
5.5 UP1core VGA_Sync: VGA Video Sync Generationp. 71
5.6 UP1core CHAR_ROM: Character Generation ROMp. 73
5.7 UP1core Keyboard: Read Keyboard Scan Codep. 74
5.8 UP1core Mouse: Mouse Cursorp. 75
6 Using VHDL for Synthesis of Digital Hardwarep. 78
6.1 VHDL Data Typesp. 78
6.2 VHDL Operatorsp. 79
6.3 VHDL Based Synthesis of Digital Hardwarep. 80
6.4 VHDL Synthesis Models of Gate Networksp. 80
6.5 VHDL Synthesis Model of a Seven-segment LED Decoderp. 81
6.6 VHDL Synthesis Model of a Multiplexerp. 83
6.7 VHDL Synthesis Model of Tri-State Outputp. 84
6.8 VHDL Synthesis Models of Flip-flops and Registersp. 84
6.9 Accidental Synthesis of Inferred Latchesp. 86
6.10 VHDL Synthesis Model of a Counterp. 86
6.11 VHDL Synthesis Model of a State Machinep. 87
6.12 VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifterp. 89
6.13 VHDL Synthesis of Multiply and Divide Hardwarep. 90
6.14 VHDL Synthesis Models for Memoryp. 91
6.15 Hierarchy in VHDL Synthesis Modelsp. 94
6.16 Using a Testbench for Verificationp. 96
6.17 For additional informationp. 97
6.18 Laboratory Exercisesp. 97
7 State Machine Design: The Electric Train Controllerp. 102
7.1 The Train Control Problemp. 102
7.2 Track Power (T1, T2, T3, and T4)p. 104
7.3 Track Direction (DA1-DA0, and DB1-DB0)p. 104
7.4 Switch Direction (SW1, SW2, and SW3)p. 105
7.5 Train Sensor Input Signals (S1, S2, S3, S4, and S5)p. 105
7.6 An Example Controller Designp. 106
7.7 VHDL Based Example Controller Designp. 110
7.8 Simulation Vector file for State Machine Simulationp. 112
7.9 Running the Train Control Simulationp. 115
7.10 Running the Video Train System (After Successful Simulation)p. 116
7.11 Laboratory Exercisesp. 117
8 A Simple Computer Design: The [mu]P 1p. 122
8.1 Computer Programs and Instructionsp. 123
8.2 The Processor Fetch, Decode and Execute Cyclep. 124
8.3 VHDL Model of the [mu]P 1p. 131
8.4 Simulation of the [mu]P1 Computerp. 134
8.5 Laboratory Exercisesp. 135
9 VGA Video Display Generationp. 140
9.1 Video Display Technologyp. 140
9.2 Video Refreshp. 140
9.3 Using a CPLD for VGA Video Signal Generationp. 143
9.4 A VHDL Sync Generation Example: UP1core VGA_SYNCp. 144
9.5 Final Output Register for Video Signalsp. 146
9.6 Required Pin Assignments for Video Outputp. 146
9.7 Video Examplesp. 147
9.8 A Character Based Video Designp. 147
9.9 Character Selection and Fontsp. 148
9.10 VHDL Character Display Design Examplesp. 151
9.11 A Graphics Memory Design Examplep. 153
9.12 Video Data Compressionp. 154
9.13 Video Color Mixing using Ditheringp. 155
9.14 VHDL Graphics Display Design Examplep. 155
9.15 Laboratory Exercisesp. 157
10 Communications: Interfacing to the PS/2 Keyboardp. 160
10.1 PS/2 Port Connectionsp. 160
10.2 Keyboard Scan Codesp. 161
10.3 Make and Break Codesp. 161
10.4 The PS/2 Serial Data Transmission Protocolp. 161
10.5 Scan Code Set 2 for the PS/2 Keyboardp. 164
10.6 The Keyboard UP1corep. 166
10.7 A Design Example Using the Keyboard UP1corep. 169
10.8 For Additional Informationp. 170
10.9 Laboratory Exercisesp. 170
11 Communications: Interfacing to the PS/2 Mousep. 172
11.1 The Mouse UP1corep. 174
11.2 Mouse Initializationp. 174
11.3 Mouse Data Packet Processingp. 175
11.4 An Example Design Using the Mouse UP1corep. 176
11.5 For Additional Informationp. 176
11.6 Laboratory Exercisesp. 176
12 Robotics: The UP1-botp. 178
12.1 The UP1-bot Designp. 178
12.2 UP1-bot Servo Drive Motorsp. 178
12.3 Modifying the Servos to make Drive Motorsp. 179
12.4 VHDL Servo Driver Code for the UP1-botp. 180
12.5 Sensors for the UP1-botp. 182
12.6 Assembly of the UP1-bot Bodyp. 190
12.7 UP1-bot FLEX Expansion B Header Pinsp. 197
12.8 An Alternative UP 1 Robot Project Based on an R/C Carp. 198
12.9 For Additional Informationp. 203
12.10 Laboratory Exercisesp. 204
13 A RISC Design: Synthesis of the MIPS Processor Corep. 210
13.1 The MIPS Instruction Set and Processorp. 210
13.2 Using VHDL to Synthesize the MIPS Processor Corep. 213
13.3 The Top-Level Modulep. 214
13.4 The Control Unitp. 217
13.5 The Instruction Fetch Stagep. 219
13.6 The Decode Stagep. 222
13.7 The Execute Stagep. 224
13.8 The Data Memory Stagep. 226
13.9 Simulation of the MIPS Designp. 227
13.10 MIPS Hardware Implementation on the UP 1 or UP 1X Boardp. 228
13.11 For Additional Informationp. 229
13.12 Laboratory Exercisesp. 230
Appendix A Generation of Pseudo Random Binary Sequencesp. 235
Appendix B MAX+PLUS II Design and Data File Extensionsp. 237
Appendix C UP 1 and UP 1X Pin Assignmentsp. 239
Appendix D The Wintim Meta Assemblerp. 243
Appendix E An Introduction to Verilog for VHDL usersp. 252
Glossaryp. 259
Indexp. 267
About the Accompanying CD-ROMp. 270