The RTL design of 32-bit RISC processor using verilog HDL

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Title:

The RTL design of 32-bit RISC processor using verilog HDL

Personal Author:

Hafizul Hasni Manab, 1987-

Publication Information:

2012

Physical Description:

xvii, 131 p. : ill. ; 30 cm.

General Note:

Supervisor :Assoc. Prof. Dr. Muhammad Nasir Ibrahim

Also available in CD-ROM : CP 028872 ra

Subject Term:

Reduced instruction set computers

Added Author:

Muhammad Nasir Ibrahim

Added Corporate Author:

Fakulti Kejuruteraan Elektrik

DSP_DISSERTATION:

Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2012

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... FKE Library	FKE30000005050	QA76.5 H34 2012 raf	Closed Access Thesis	UTM Master Thesis (Closed Access)	Searching... Unknown
Searching... Perpustakaan Raja Zarith Sofiah	30000010299111	QA76.5 H34 2012 raf	Closed Access Thesis	UTM Master Thesis (Closed Access)	Searching... Unknown

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