Sub-threshold design for ultra low-power systems

Although energy dissipation has improved with each new technology node, because SoCs are integrating tens of million devices on-chip, the energy ex pended per operation has become a critical consideration in digital and ana log integrated circuits. The focus of this book is sub-threshold circuit design, which involves scaling voltages below the device thresholds. In this region, the energy per operation cair be reduced by an order of magnitude compared to conventional operation but at the cost of circuit performance. In many emerging applications such as self-powered RFID, wireless sensors networks, and portable devices (PDAs, medical monitoring, etc. ), the overall battery life time is the primary design metric. Sub-threshold design can also be applied to burst mode applications (e. g. , a cell-phone processor) where the process spends a significant amount of time in the standby mode. The supply voltage can be reduced to the deep sub-threshold region, dramatically saving power in logic and memory. Extremely low-power design was first explored in the 1970s for the design of applications such as wristwatch and calculator circuits. Dr. Eric Vittoz pioneered the design and modeling of weak-inversion circuits. In this book, Eric provides his perspective on the evolution of sub-threshold circuit design. Dr. Eric Vittoz and Dr. Christian Enz introduce key models necessary for the design and optimization of weak inversion circuits. Design using weak inversion has been widely adopted in analog circuits, and Eric introduces the key design considerations.

Eric A. VittozEric A. Vittoz and Christian C. EnzJoyce KwongEric A. Vittoz

1 Introduction	p. 1
1.1 Energy-Constrained Applications	p. 2
1.1.1 Micro-sensor Networks and Nodes	p. 2
1.1.2 Radio Frequency Identification (RFID)	p. 3
1.1.3 Low-power Digital Signal Processor (DSP) and Microcontroller Units (MCU)	p. 3
1.2 System requirements	p. 4
1.2.1 Battery Lifetimes	p. 4
1.2.2 Energy Harvesting	p. 4
1.3 Book Summary	p. 5
2 Origins of Weak Inversion (or Sub-threshold) Circuit Design	p. 7
3 Survey of Low-voltage Implementations	p. 11
3.1 Technology Scaling	p. 11
3.2 Low-voltage Logic Designs	p. 14
3.3 History of Minimum Voltage	p. 17
3.4 History of Minimum Energy	p. 20
3.5 Survey of Sub-threshold CMOS Circuits	p. 22
4 Minimizing Energy Consumption	p. 25
4.1 Energy-Performance Contours	p. 25
4.1.1 Variable Activity Factor Circuit	p. 25
4.1.2 Energy-Performance Contours	p. 26
4.1.3 Activity Factor	p. 28
4.2 Modeling Minimum Energy Consumption	p. 30
4.2.1 Sub-Threshold Leakage Current Models	p. 30
4.2.2 Other Components of Current	p. 34
4.2.3 Minimum Energy Point Model	p. 35
4.3 Minimum Energy Point Dependencies	p. 42
4.3.1 Operating Scenario	p. 42
4.3.2 Temperature	p. 45
4.3.3 Architecture	p. 46
5 EKV Model of the MOS Transistor	p. 49
5.1 Introduction and Definitions	p. 49
5.2 Density of Mobile Charge	p. 50
5.2.1 Threshold Function	p. 50
5.2.2 Approximation in Strong Inversion	p. 52
5.2.3 General Case	p. 53
5.2.4 Approximation in Weak Inversion	p. 54
5.3 Drain Current and Modes of Operation	p. 54
5.3.1 Charge-Current Relationship	p. 54
5.3.2 Forward and Reverse Components	p. 55
5.3.3 General Current Expression	p. 56
5.3.4 Modes of Operation and Inversion Coefficient	p. 57
5.3.5 Output Characteristics and Saturation Voltage	p. 58
5.3.6 Weak Inversion Approximation	p. 59
5.4 Small-Signal Model	p. 59
5.4.1 Transconductances	p. 59
5.4.2 Residual Conductance in Saturation and Maximum Voltage Gain	p. 61
5.4.3 Small-Signal AC Model	p. 61
5.5 Transistor Operated As a Pseudo-Resistor	p. 62
5.6 Noise	p. 63
5.6.1 Noise model	p. 63
5.6.2 Channel Noise	p. 64
5.6.3 Interface Noise	p. 65
5.6.4 Total Noise	p. 65
5.7 Temperature effects	p. 65
5.8 Non-ideal effects	p. 67
5.8.1 Mismatch	p. 67
5.8.2 Polysilicon Gate Depletion	p. 69
5.8.3 Band Gap Widening	p. 70
5.8.4 Gate Leakage	p. 71
5.8.5 Drain-Induced Barrier Lowering (DIBL)	p. 72
6 Digital Logic	p. 75
6.1 Inverter Operation in Sub-threshold	p. 75
6.1.1 Sub-threshold Inverter Delay	p. 75
6.1.2 Sub-threshold Voltage Transfer Characteristics (VTCs)	p. 77
6.1.3 Inverter Sizing for Minimum Energy	p. 82
6.2 Sub-threshold CMOS Standard Cell Library	p. 83
6.2.1 Parallel Devices	p. 84
6.2.2 Stacked Devices	p. 86
6.2.3 Flip-flops	p. 87
6.2.4 Ratioed Circuits	p. 88
6.2.5 Measured Results from Test Chip	p. 89
6.3 Logic Families in Sub-threshold	p. 92
6.3.1 Process Variation in Sub-threshold Logic	p. 92
6.3.2 Evaluating Logic Styles in the Context of Variations	p. 95
7 Sub-threshold Memories	p. 103
7.1 Register Files	p. 103
7.1.1 Write Port and Memory Cell	p. 104
7.1.2 Read Bitline Architectures	p. 105
7.1.3 Sub-threshold Register File	p. 114
7.2 Sub-threshold SRAM	p. 115
7.2.1 SRAM Overview	p. 116
7.2.2 6-Transistor SRAM Bitcell in Sub-threshold	p. 123
7.2.3 Write Operation	p. 124
7.2.4 Read Operation	p. 127
7.2.5 Static Noise Margin in sub-threshold	p. 129
7.2.6 A Sub-threshold Bit-cell Design	p. 131
7.2.7 65nm Sub-threshold SRAM Test Chip	p. 139
8 Analog Circuits in Weak Inversion	p. 147
8.1 Introduction	p. 147
8.2 Minimum Saturation Voltage	p. 148
8.2.1 Current Mirrors	p. 148
8.2.2 Cascode Mirrors	p. 148
8.2.3 Low-Voltage Amplifiers	p. 150
8.3 Maximum Transconductance-to-Current Ratio	p. 151
8.3.1 Differential Pair	p. 151
8.3.2 Single-Stage Operational Transconductance Amplifiers (OTA)	p. 154
8.4 Exponential Characteristics	p. 156
8.4.1 Voltage and Current Reference	p. 156
8.4.2 Amplitude Regulator	p. 157
8.4.3 Translinear Circuits	p. 158
8.4.4 Log-Domain Filters [177, 178, 179, 180]	p. 161
8.5 Pseudo-Resistor	p. 162
8.5.1 Analysis of Circuits	p. 162
8.5.2 Emulation of Variable Resistive Networks	p. 163
9 System Examples	p. 167
9.1 A Sub-threshold FFT Processor	p. 167
9.1.1 The Fast Fourier Transform	p. 168
9.1.2 Energy-Aware Architectures	p. 169
9.1.3 Minimum Energy Point Analysis	p. 170
9.1.4 Measurements	p. 171
9.2 Ultra-Dynamic Voltage Scaling	p. 173
9.2.1 DVS and Local Voltage Dithering	p. 174
9.2.2 Ultra-Dynamic Voltage Scaling (UDVS) Test Chip	p. 178
9.2.3 UDVS System Considerations	p. 184
A Acronyms	p. 191
References	p. 193
Index	p. 207

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