Cover image for Design & implementation (VLSI) of an all digital phase locked loop (ADPLL)
Title:
Design & implementation (VLSI) of an all digital phase locked loop (ADPLL)
Personal Author:
Publication Information:
Skudai : Universiti Teknologi Malaysia, 2005
Physical Description:
xix, 96 p. : ill ; 30 cm.
DSP_DISSERTATION:
Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2005

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FKE30000002999 TK7874.75 C47 2005 Closed Access Thesis UTM Project Paper (Closed Access)
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30000010096311 TK7874.75 C47 2005 Closed Access Thesis UTM Project Paper (Closed Access)
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