Cover image for Digital clocks for synchronization and communications
Title:
Digital clocks for synchronization and communications
Personal Author:
Publication Information:
Norwood, MA : Artech House, 2003
ISBN:
9781580535069

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30000010019127 TK7868.T5 K54 2003 Open Access Book Book
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Summary

Summary

This handbook seeks to provide an in-depth and practical understanding of the digital clock technologies used in building today's telecommunications networks. Covering critical details on the PLL (phase-locked loop) technique for clock synchronization and generation, and the DDS (direct digital synthesizer) technique for clock generation, the work is designed to help the reader achieve synchronization in high-speed networks and frequency stabilization in portable equipment. Discussing both wired and wireless networks, the volume looks at the combination of circuits and systems to give you a more thorough understanding of important design requirements.


Author Notes

Masami Kihara holds a B.S. in electrical engineering and Ph.D. in engineering from Nihon University.

Mr. Kihara, a visiting professor at the Helsinki University of Technology, has extensive practical experience designing frequency/time systems used in the commercial network of Nippon Telegraph and Telephone Corporation.

050


Table of Contents

Preface
Guide to the Book
Introduction to Clocks
What is a Clock
Clock Sharing
Frequency Synchronization Technology
Frequency Generation Technology
Basic Clock Synchronization and Generation
Clock Frequency/Phase Locking
Clock Synthesis
Trends in Frequency Synchronization and Generation Circuits
Signal Processing Fundamentals
Signal Processing and Systems
Digital Signal Processing
Digital Filter
Introduction to PLL
Basic Mechanism in Phase Synchronization
Element Operation
Classification of the PLL
PLL Applications
PLL Characteristics
PLL Characteristic Analysis
Basic Analysis of PLL Characteristics
Basic Characteristics
Transfer Function and Response Characteristics of the First Order Loop PLL
Transfer Function and Second Order Loop Response
Simulation of Digital PLL
Transfer Function Analysis
Transient Response Simulation
Steady-State Phase Error Simulation
Clock Systems in Networks
Wired Systems
Wireless Systems
Digital Synchronization: System Design Basic Design
Basic Configuration
Digital-Controlled Oscillator Design
Digital-Processing Phase Comparator
Digital Control
Frequency Range of the Controlled Oscillator
Time Constant and Synchronization Range
Loop Filter Configuration and Transfer Function
Noise Performance
Operation Against Input Problems
PLL LSI
PLL in Transmission Interfaces
Basic Configuration of Transmission Clock Recovery Circuit
Signal Receiving and Regeneration Circuit Using PLL
CDR Based on the PLL
Transmission Clock Generation Circuit
LSIs for Wireless Systems
Frequency Generation System
The Need for Frequency Generation
The Evolution Frequency Synchronization and Generation Systems
Ideal Clock Generation Using Digital Signal Processing
DDS Characteristics
DDS Circuit Configuration and Characteristics
Basic Parameters
Spectrum
New Design Methodology
DDS Applications
DDS Trend
Synthesizer
Combination of DDS and PLL
Atomic Frequency Standard
DDS in Wireless Systems
Noise in Clocks
Frequency Stability and Noise
Relationship between Sine Wave and Noise
Noise Processing
Phase Noise and Frequency Noise
Frequency Component of Noise
Other Measures for Spectrum Analysis
Variance and Power Spectral Density
Noise Measurement
Variance Measurement in Time Domain
Spectrum Measurement in Frequency Domain
Noise Characteristics in Circuits and Devices
Oscillator Noise Characteristics
Microwave Devices
Divider
Operational and Environmental Effects on Noise Characteristics
Noise Characteristics in Wired Transmission Systems
Noise Characteristics in Radio Systems
Appendixes