Transient-induced latchup in CMOS integrated circuits

The book all semiconductor device engineers must read to gain a practical feel for latchup-induced failure to produce lower-cost and higher-density chips.

Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process.

Presents real cases and solutions that occur in commercial CMOS IC chips Equips engineers with the skills to conserve chip layout area and decrease time-to-market Written by experts with real-world experience in circuit design and failure analysis Distilled from numerous courses taught by the authors in IC design houses worldwide The only book to introduce TLU under system-level ESD and EFT tests

This book is essential for practicing engineers involved in IC design, IC design management, system and application design, reliability, and failure analysis. Undergraduate and postgraduate students, specializing in CMOS circuit design and layout, will find this book to be a valuable introduction to real-world industry problems and a key reference during the course of their careers.

Author Notes

Ming-Dou Ker is a Professor of Electronics Engineering at National Chiao-Tung University, where he also serves as the Director of the College of Electrical Engineering and Computer Science Master's Degree Program. He is also the Associate Executive Director of Taiwan's National Science and Technology Program on System-on-Chip, and in the past has worked as the Department Manager in the VLSI Design Division of the Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI). Ker has published 300 technical papers in international journals and conferences related to reliability and quality design for circuits and systems in CMOS technology. He has also proposed many inventions to improve reliability and quality of integrated circuits, generating 125 U.S. patents and 135 Taiwan patents in Taiwan. As an active member of the global IEEE community, he has been Technical Program Committee and Session Chair of numerous international conferences and was selected as the Distinguished Lecturer in IEEE Circuits and Systems Society for year 2006-2007. In 2007 Ker was named IEEE Fellow for his contributions to electrostatic protection in integrated circuits, and performance optimization of VLSI micro-systems. He holds a Ph.D. from the Institute of Electronics, National Chiao-Tung University.

Preface	p. xi
1 Introduction	p. 1
1.1 Latchup Overview	p. 1
1.2 Background of TLU	p. 7
1.3 Categroies of TLU-Triggering Modes	p. 7
1.3.1 Power-On Transition	p. 7
1.3.2 Transmission Line Reflections	p. 8
1.3.3 Supply Voltage Overshoots	p. 11
1.3.4 Cable Discharge Event	p. 12
1.3.5 System-Level ESD Event	p. 13
1.4 TLU Standard Practice	p. 16
References	p. 19
2 Physical Mechanism of TLU under the System-Level ESD Test	p. 23
2.1 Background	p. 23
2.2 TLU in the System-Level ESD Test	p. 24
2.3 Test Structure	p. 26
2.4 Measurement Setup	p. 28
2.5 Device Simulation	p. 30
2.5.1 Latchup DC I-V Characteristics	p. 32
2.5.2 Negative VCharge	p. 32
2.5.3 Positive VCharge	p. 35
2.5.4 A More Realistic Case	p. 37
2.6 TLU Measurement	p. 38
2.6.1 Latchup DC I-V Characteristics	p. 38
2.6.2 Negative VCharge	p. 39
2.6.3 Positive VCharge	p. 39
2.7 Discussion	p. 41
2.7.1 Dominant Parameter to Induce TLU	p. 41
2.7.2 Transient Responses on the Minority Carriers Stored within the SCR	p. 43
2.8 Conclusion	p. 44
References	p. 44
3 Component-Level Measurement for TLU under System-Level ESD Considerations	p. 47
3.1 Background	p. 47
3.2 Component-Level TLU Measurement Setup	p. 48
3.3 Influence of the Current-Blocking Diode and Current-Limiting Resistance on the Bipolar Trigger Waveforms	p. 49
3.3.1 Positive VCharge	p. 51
3.3.2 Negative VCharge	p. 51
3.4 Influence of the Current-Blocking Diode and Current-Limiting Resistance on the TLU Level	p. 54
3.4.1 Latchup DC I-V Characteristics	p. 54
3.4.2 Positive TLU Level	p. 55
3.4.3 Negative TLU Level	p. 57
3.5 Verification of Device Simulation	p. 59
3.5.1 Dependences of the Current-Blocking Diode on TLU Level	p. 59
3.5.2 Dependences of Current-Limiting Resistance of TLU Level	p. 62
3.6 Suggested Component-Level TLU Measurement Setup	p. 62
3.7 TLU Verification on Real Circuits	p. 63
3.8 Evaluation on Board-Level Noise Filters to Suppress TLU	p. 66
3.8.1 TLU Transient Waveforms of the Ring Oscillator	p. 69
3.8.2 TLU Level of the Ring Oscillator with Noise Filters	p. 70
3.9 Conclusion	p. 72
References	p. 73
4 TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits	p. 75
4.1 Examples of Different DFreq and DFactor in the System-Level ESD Test	p. 76
4.2 TLU Dependency on DFreq and DFactor	p. 80
4.2.1 Relations between DFactor and Minimum Positive (Negative) VP to Initiate TLU	p. 80
4.2.2 Relations between DFreq and Minimum Positive (Negative) VP to Initiate TLU	p. 82
4.2.3 Relations between DFactor and Minimum (Maximum) DFreq to Initiate TLU	p. 84
4.3 Experimental Verification on TLU	p. 86
4.4 Suggested Guidelines for TLU Prevention	p. 89
4.5 Conclusion	p. 92
References	p. 93
5 TLU in CMOS ICs in the Electrical Fast Transient Test	p. 95
5.1 Electrical Fast Transient Test	p. 95
5.2 Test Structure	p. 98
5.3 Experimental Measurements	p. 102
5.3.1 Negative EFT Voltage	p. 103
5.3.2 Positive EFT Voltage	p. 104
5.3.3 Physical Mechanism of TLU in the EFT Test	p. 105
5.4 Evaluation on Board-Level Noise Filters to Suppress TLU in the EFT Test	p. 106
5.4.1 Capacitor Filter, LC-Like Filter, and ?-Section Filter	p. 106
5.4.2 Ferrite Bead, TVS, and Hybrid Type Filiters	p. 109
5.4.3 Discussion	p. 111
5.5 Conclusion	p. 112
References	p. 112
6 Methodology on Extracting Compact Layout Rules for Latchup Prevention	p. 113
6.1 Introduction	p. 113
6.2 Latchup Test	p. 114
6.2.1 Latchup Testing Classification	p. 114
6.2.2 Trigger Current Test	p. 115
6.2.3 VSupply Over-Voltage Test	p. 117
6.3 Extraction of Layout Rules for I/O Cells	p. 121
6.3.1 Latchup in I/O Cells	p. 121
6.3.2 Design of Test Structure for I/O Cells	p. 124
6.3.3 Latchup Immunity Dependency of I/O Cells	p. 125
6.4 Extraction of Layout Rules for Internal Circuits	p. 129
6.4.1 Latchup in Internal Circuits	p. 129
6.4.2 Design of Test Structure for Internal Circuits	p. 130
6.4.3 Latchup Immunity Dependency of the Internal Circuits	p. 131
6.5 Extraction of Layout Rules between I/O Cells and Internal Ciruits	p. 136
6.5.1 Layout Considerations between I/O Cells and Internal Circuits	p. 136
6.5.2 Design of Test Structure between I/O Cells and Internal Circuits	p. 139
6.5.3 Threshold Latchup Trigger Current Dependency	p. 141
6.6 Conclusion	p. 148
References	p. 149
7 Special Layout Issues for Latchup Prevention	p. 151
7.1 Latchup between Two Different Power Domanins	p. 151
7.1.1 Practical Examples	p. 152
7.1.2 Suggested Solutions	p. 156
7.2 Latchup in Internal Circuits Adjacent to Power-Rail ESD Clamp Circuits	p. 156
7.2.1 Practical Examples	p. 157
7.2.2 Suggested Solutions	p. 159
7.3 Unexpected Trigger Point to Initiate Latchup in Internal Circuits	p. 159
7.3.1 Practical Examples	p. 161
7.3.2 Suggested Solutions	p. 165
7.4 Other Unexpected Latchup Paths in CMOS ICs	p. 165
7.5 Conclusion	p. 167
References	p. 168
8 TLU Prevention in Power-Rail ESD Clamp Circuits	p. 169
8.1 In LV CMOS ICs	p. 169
8.1.1 Power-Rail ESD Clamp Circuits	p. 171
8.1.2 TLU-Like Issues in LV Power-Rail ESD Clamp Ciricuits	p. 174
8.1.3 Design of TLU-Free Power-Rail ESD Clamp Circuits	p. 183
8.2 In HV CMOS ICs	p. 189
8.2.1 High-Voltage ESD Protection Devices	p. 190
8.2.2 Design of TLU-Free Power-Rail ESD Clamp Circuits	p. 197
8.3 Conclusion	p. 204
References	p. 205
9 Summary	p. 207
9.1 TLU in CMOS ICs	p. 207
9.2 Extraction of Compact and Safe Layout Rules for Latchup Prevention	p. 209
Appendix A Practical Application-Extractions of Latchup Design Rules in a 0.18-µm 1.8 V/3.3 V Silicided CMOS Process	p. 211
A.1 for I/O Cells	p. 211
A.1.1 Nomenclature	p. 211
A.1.2 I/O Cells with a Double Guard Rings	p. 212
A.1.3 I/O Cells with a Single Guard Ring	p. 215
A.1.4 Suggested Layout Rules for I/O Cells	p. 221
A.2 for Internal Circuits	p. 223
A.2.1 Nomenclature	p. 223
A.2.2 Design of Test Structures	p. 223
A.2.3 Latchup Immunity Dependency of Internal Circuits	p. 224
A.2.4 Siggested Layout Rules for Internal Circuits	p. 226
A.3 for between I/O and Internal Circuits	p. 226
A.3.1 Normenclature	p. 226
A.3.2 I/O and Internal Circuits (SCR)	p. 227
A.3.3 I/O and the Internal Circuits (Ring Oscillator)	p. 233
A.3.4 Suggested Layout Rules for between I/O and the Internal Circuits	p. 235
A.4 For Circuits across Two Different Power Domains	p. 237
A.4.1 Nomenclature	p. 237
A.4.2 Design of Test Structures	p. 237
A.4.3 Latchup Immunity Dependency between Two Different Power Domains	p. 241
A.4.4 Suggested Layout Rules between Two Different Power Domains	p. 242
A.5 Suggested Layout Guidelines	p. 244
A.5.1 Latchup Design Guidelines for I/O Circuits\|244
A.5.2 Latchup Design Guidelines for between I/O and the Internal Circuits	p. 245
A.5.3 Latchup Design Guidelines for Internal Circuits	p. 246
A.5.4 Latchup Design Guidelines for Circuits across Two Different Power Domains	p. 246
Index	p. 247

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