Title:
PCI express system architecture
Personal Author:
Publication Information:
Boston : Addison-Wesley, 2004
ISBN:
9780321156303
Available:*
Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
---|---|---|---|---|---|
Searching... | 30000010049412 | QA76.9.A73 P43 2004 | Open Access Book | Book | Searching... |
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Summary
Summary
••PCI EXPRESS is considered to be the most general purpose bus so it should appeal to a wide audience in this arena.•Today's buses are becoming more specialized to meet the needs of the particular system applications, building the need for this book.•Mindshare and their only competitor in this space, Solari, team up in this new book.
Author Notes
Ravi Budruk is a senior staff engineer and instructor with MindShare, Inc., where he has trained hundreds of engineers
Don Anderson is an expert on digital electronics and system design. He passes on his wealth of experience by training engineers, programmers, and technicians at MindShare, Inc.
Tom Shanley is President of MindShare, Inc.
Excerpts
Excerpts
The MindShare Architecture Series The MindShare Architecture book series currently includes the books listed below. The entire book series is published by Addison-Wesley. Books about Processor Architecture: 80486 System Architecture, Third Edition , 0-201-40994-1 Pentium Processor System Architecture, Second Edition , 0-201-40992-5 Pentium Pro and Pentium II System Architecture, Second Edition , 0-201-30973-4 Power PC System Architecture , 0-201-40990-9 Books About Bus Architecture: PCI System Architecture, Fourth Edition , 0-201-30974-2 PCI-X System Architecture , 0-201-72682-3 EISA System Architecture , 0-201-40995-X--Out-of-print Firewire System Architecture, Second Edition: IEEE 1394a , 0-201-48535-4 ISA System Architecture, Third Edition , 0-201-40996-8 Universal Serial Bus System Architecture 2.0 , 0-201-46137-4 HyperTransport™ System Architecture , 0-321-16845-3 PCI Express System Architecture , 0-321-15630-7 Books About Network Architecture: Network Architecture Infiniband Network Architecture , 0-321-11765-4 Books About Other Architectures: PCMCIA System Architecture, Second Edition: 16-Bit PC Cards , 0-201-40991-7 CardBus System Architecture , 0-201-40997-6 Plug and Play System Architecture , 0-201-41013-3 Protected Mode Software Architecture , 0-201-55447-X AGP System Architecture , 0-201-37964-3 Cautionary Note The reader should keep in mind that MindShare's book series often details rapidly evolving technologies, as is the case with PCI Express. This being the case, it should be recognized that the book is a "snapshot" of the state of the technology at the time the book was completed. We make every attempt to produce our books on a timely basis, but the next revision of the specification is not introduced in time to make necessary changes. This PCI Express book complies with revision 1.0a of the PCI Express™ Base Specification released and trademarked by the PCI Special Interest Group. Several expansion card form-factor specifications are planned for PCI Express, but only the Electro-mechanical specification, revision 1.0 was released when this book was completed. However, the chapter covering the Card Electromechanical topic reviews several form-factors that were under development at the time of writing. Intended Audience This book is intended for use by hardware and software design and support personnel. The tutorial approach taken may also make it useful to technical personnel not directly involved design, verification, and other support functions. Prerequisite Knowledge It is recommended that the reader has a reasonable background in PC architecture, including experience or knowledge of an I/O bus and related protocol. Because PCI Express maintains several levels of compatibility with the original PCI design, critical background information regarding PCI has been incorporated into this book. However, the reader may find it beneficial to read the MindShare publication entitled PCI System Architecture , which focusses on and details the PCI architecture. Topics and Organization Topics covered in this book and the flow of the book are as follows: Part 1: Background and Comprehensive Overview. Provides an architectural perspective of the PCI Express technology by comparing and contrasting it with the PCI and PCI-X buses. It also introduces the major features of the PCI Express architecture. Part 2: PCI Express Transaction Protocol. Includes packet format and field definition and use, along with transaction and link layer functions. Part 3: Physical Layer Description. Describes the physical layer functions, link training and initialization, reset, and electrical signaling. Part 4: Power-Related Topics. Discusses Power Budgeting and Power Management. Part 5: Optional Topics. Discusses the major features of PCI Express that are optional, including Hot Plug and Expansion Card implementation details. Part 6: PCI Express Configuration. Discusses the configuration process, accessing configuration space, and details the content and use of all configuration registers. Appendix: Test, Debug, and Verification Markets & Applications for the PCI Express™ Architecture Implementing Intelligent Adapters and Multi-Host Systems With PCI Express™ Technology PCI Express Class Codes Legacy Support for Locking Documentation Conventions This section defines the typographical convention used throughout this book. PCI Express™ PCI Express™ is a trademark of the PCI SIG. This book takes the liberty of abbreviating PCI Express as "PCI-XP" primarily in illustration where limited space is an issue. Hexadecimal Notation All hex numbers are followed by a lower case "h." For example: 89F2BD02h 0111h Binary Notation All binary numbers are followed by a lower case "b." For example: 1000 1001 1111 0010b 01b Decimal Notation Number without any suffix are decimal. When required for clarity, decimal numbers are followed by a lower case "d." Examples: 9 15 512d Bits Versus Bytes Notation This book represents bit with lower case "b" and bytes with an upper case "B." For example: Megabits/second = Mb/s Megabytes/second = MB/s Bit Fields Groups bits are represented with the high-order bits first followed by the loworder bits and enclosed by brackets. For example: 7:0 = bits 0 through 7 Active Signal States Signals that are active low are followed by #, as in PERST# and WAKE#. Active high signals have no suffix, such as POWERGOOD. Visit Our Web Site Our web site lists all of our courses and the delivery options available for each course: Information on MindShare courses: Self-paced DVDs and CDs Live web-delivered classes Live on-site classes. Free short courses on selected topics Technical papers Errata for a number of our books All of our books are listed and can be ordered in bound or e-book versions. www.mindshare.com We Want Your Feedback MindShare values you comments and suggestions. Contact us at: Phone: (719) 487-1417 or within the U.S. (800) 633-1440 Fax: (719) 487-1434 (Fax) Technical seminars: E-mail nancy@mindshare.com Technical questions: E-mail don@mindshare.com or tom@mindshare.com General information: E-mail info@mindshare.com Mailing Address: MindShare, Inc. 4285 Slash Pine Drive Colorado Springs, CO 80908 0321156307P08262003 Excerpted from PCI Express System Architecture by Ravi Budruk, Don Anderson, Tom Shanley, MindShare, Inc. Staff, Solari All rights reserved by the original copyright owners. Excerpts are provided for display purposes only and may not be reproduced, reprinted or distributed without the written permission of the publisher.Table of Contents
About This Book | |
The MindShare Architecture Series | p. 1 |
Cautionary Note | p. 2 |
Intended Audience | p. 2 |
Prerequisite Knowledge | p. 3 |
Topics and Organization | p. 3 |
Documentation Conventions | p. 4 |
PCI Express | p. 4 |
Hexadecimal Notation | p. 4 |
Binary Notation | p. 4 |
Decimal Notation | p. 4 |
Bits Versus Bytes Notation | p. 5 |
Bit Fields | p. 5 |
Active Signal States | p. 5 |
Visit Our Web Site | p. 5 |
We Want Your Feedback | p. 6 |
Part 1 The Big Picture | |
Chapter 1 Architectural Perspective | |
Introduction To PCI Express | p. 9 |
Predecessor Buses Compared | p. 11 |
I/O Bus Architecture Perspective | p. 16 |
The PCI Express Way | p. 41 |
PCI Express Specifications | p. 54 |
Chapter 2 Architecture Overview | |
Introduction to PCI Express Transactions | p. 55 |
PCI Express Device Layers | p. 69 |
Example of a Non-Posted Memory Read Transaction | p. 96 |
Hot Plug | p. 101 |
PCI Express Performance and Data Transfer Efficiency | p. 101 |
Part 2 Transaction Protocol | |
Chapter 3 Address Spaces & Transaction Routing | |
Introduction | p. 106 |
Two Types of Local Link Traffic | p. 108 |
Transaction Layer Packet Routing Basics | p. 113 |
Applying Routing Mechanisms | p. 121 |
Plug-And-Play Configuration of Routing Options | p. 135 |
Chapter 4 Packet-Based Transactions | |
Introduction to the Packet-Based Protocol | p. 154 |
Transaction Layer Packets | p. 156 |
Data Link Layer Packets | p. 198 |
Chapter 5 ACK/NAK Protocol | |
Reliable Transport of TLPs Across Each Link | p. 210 |
Elements of the ACK/NAK Protocol | p. 212 |
ACK/NAK DLLP Format | p. 219 |
ACK/NAK Protocol Details | p. 220 |
Error Situations Reliably Handled by ACK/NAK Protocol | p. 239 |
ACK/NAK Protocol Summary | p. 241 |
Recommended Priority To Schedule Packets | p. 244 |
Some More Examples | p. 244 |
Switch Cut-Through Mode | p. 248 |
Chapter 6 QoS/TCs/VCs and Arbitration | |
Quality of Service | p. 252 |
Perspective on QOS/TC/VC and Arbitration | p. 255 |
Traffic Classes and Virtual Channels | p. 256 |
Arbitration | p. 263 |
Chapter 7 Flow Control | |
Flow Control Concept | p. 286 |
Flow Control Buffers | p. 288 |
Introduction to the Flow Control Mechanism | p. 290 |
Flow Control Packets | p. 293 |
Operation of the Flow Control Model - An Example | p. 294 |
Infinite Flow Control Advertisement | p. 301 |
The Minimum Flow Control Advertisement | p. 303 |
Flow Control Initialization | p. 304 |
Flow Control Updates Following FC_INIT | p. 308 |
Chapter 8 Transaction Ordering | |
Introduction | p. 316 |
Producer/Consumer Model | p. 317 |
Native PCI Express Ordering Rules | p. 318 |
Relaxed Ordering | p. 319 |
Modified Ordering Rules Improve Performance | p. 322 |
Support for PCI Buses and Deadlock Avoidance | p. 326 |
Chapter 9 Interrupts | |
Two Methods of Interrupt Delivery | p. 330 |
Message Signaled Interrupts | p. 331 |
Legacy PCI Interrupt Delivery | p. 342 |
Devices May Support Both MSI and Legacy Interrupts | p. 352 |
Special Consideration for Base System Peripherals | p. 353 |
Chapter 10 Error Detection and Handling | |
Background | p. 356 |
Introduction to PCI Express Error Management | p. 356 |
Sources of PCI Express Errors | p. 361 |
Error Classifications | p. 368 |
How Errors are Reported | p. 370 |
Baseline Error Detection and Handling | p. 372 |
Advanced Error Reporting Mechanisms | p. 382 |
Summary of Error Logging and Reporting | p. 392 |
Part 3 The Physical Layer | |
Chapter 11 Physical Layer Logic | |
Physical Layer Overview | p. 397 |
Transmit Logic Details | p. 403 |
Receive Logic Details | p. 437 |
Physical Layer Error Handling | p. 450 |
Chapter 12 Electrical Physical Layer | |
Electrical Physical Layer Overview | p. 453 |
High Speed Electrical Signaling | p. 455 |
LVDS Eye Diagram | p. 470 |
Transmitter Driver Characteristics | p. 477 |
Input Receiver Characteristics | p. 480 |
Electrical Physical Layer State in Power States | p. 481 |
Chapter 13 System Reset | |
Two Categories of System Reset | p. 487 |
Reset Exit | p. 496 |
Link Wakeup from L2 Low Power State | p. 497 |
Chapter 14 Link Initialization & Training | |
Link Initialization and Training Overview | p. 500 |
Ordered-Sets Used During Link Training and Initialization | p. 504 |
Link Training and Status State Machine (LTSSM) | p. 508 |
Detailed Description of LTSSM States | p. 513 |
LTSSM Related Configuration Registers | p. 549 |
Part 4 Power-Related Topics | |
Chapter 15 Power Budgeting | |
Introduction to Power Budgeting | p. 557 |
The Power Budgeting Elements | p. 558 |
Slot Power Limit Control | p. 562 |
The Power Budget Capabilities Register Set | p. 564 |
Chapter 16 Power Management | |
Introduction | p. 568 |
Primer on Configuration Software | p. 569 |
Function Power Management | p. 585 |
Introduction to Link Power Management | p. 606 |
Link Active State Power Management | p. 608 |
Software Initiated Link Power Management | p. 629 |
Link Wake Protocol and PME Generation | p. 638 |
Part 5 Optional Topics | |
Chapter 17 Hot Plug | |
Background | p. 650 |
Hot Plug in the PCI Express Environment | p. 651 |
Elements Required to Support Hot Plug | p. 655 |
Card Removal and Insertion Procedures | p. 658 |
Standardized Usage Model | p. 663 |
Standard Hot Plug Controller Signaling Interface | p. 668 |
The Hot-Plug Controller Programming Interface | p. 670 |
Slot Numbering | p. 681 |
Quiescing Card and Driver | p. 681 |
The Primitives | p. 682 |
Chapter 18 Add-in Cards and Connectors | |
Introduction | p. 686 |
Form Factors Under Development | p. 703 |
Part 6 PCI Express Configuration | |
Chapter 19 Configuration Overview | |
Definition of Device and Function | p. 712 |
Definition of Primary and Secondary Bus | p. 714 |
Topology Is Unknown At Startup | p. 714 |
Each Function Implements a Set of Configuration Registers | p. 715 |
Host/PCI Bridge's Configuration Registers | p. 716 |
Configuration Transactions Are Originated by the Processor | p. 718 |
Configuration Transactions Are Routed Via Bus, Device, and Function Number | p. 718 |
How a Function Is Discovered | p. 719 |
How To Differentiate a PCI-to-PCI Bridge From a Non-Bridge Function | p. 719 |
Chapter 20 Configuration Mechanisms | |
Introduction | p. 722 |
PCI-Compatible Configuration Mechanism | p. 723 |
PCI Express Enhanced Configuration Mechanism | p. 731 |
Type 0 Configuration Request | p. 732 |
Type 1 Configuration Request | p. 733 |
Example PCI-Compatible Configuration Access | p. 735 |
Example Enhanced Configuration Access | p. 736 |
Initial Configuration Accesses | p. 738 |
Chapter 21 PCI Express Enumeration | |
Introduction | p. 741 |
Enumerating a System With a Single Root Complex | p. 742 |
Enumerating a System With Multiple Root Complexes | p. 753 |
A Multifunction Device Within a Root Complex or a Switch | p. 758 |
An Endpoint Embedded in a Switch or Root Complex | p. 761 |
Memorize Your Identity | p. 763 |
Root Complex Register Blocks (RCRBs) | p. 765 |
Miscellaneous Rules | p. 766 |
Chapter 22 PCI Compatible Configuration Registers | |
Header Type 0 | p. 770 |
Header Type 1 | p. 802 |
PCI-Compatible Capabilities | p. 845 |
Chapter 23 Expansion ROMs | |
ROM Purpose--Device Can Be Used In Boot Process | p. 872 |
ROM Detection | p. 872 |
ROM Shadowing Required | p. 875 |
ROM Content | p. 875 |
Execution of Initialization Code | p. 885 |
Introduction to Open Firmware | p. 888 |
Chapter 24 Express-Specific Configuration Registers | |
Introduction | p. 894 |
PCI Express Capability Register Set | p. 896 |
PCI Express Extended Capabilities | p. 929 |
RCRB | p. 957 |
Appendices | |
Appendix A Test, Debug and Verification | p. 963 |
Appendix B Markets & Applications for the PCI Express Architecture | p. 989 |
Appendix C Implementing Intelligent Adapters and Multi-Host Systems With PCI Express Technology | p. 999 |
Appendix D Class Codes | p. 1019 |
Appendix E Locked Transactions Series | p. 1033 |
Index | p. 1043 |