Skip to:Content
|
Bottom
Cover image for PCI express system architecture
Title:
PCI express system architecture
Personal Author:
Publication Information:
Boston : Addison-Wesley, 2004
ISBN:
9780321156303

Available:*

Library
Item Barcode
Call Number
Material Type
Item Category 1
Status
Searching...
30000010049412 QA76.9.A73 P43 2004 Open Access Book Book
Searching...

On Order

Summary

Summary

••PCI EXPRESS is considered to be the most general purpose bus so it should appeal to a wide audience in this arena.•Today's buses are becoming more specialized to meet the needs of the particular system applications, building the need for this book.•Mindshare and their only competitor in this space, Solari, team up in this new book.


Author Notes

Ravi Budruk is a senior staff engineer and instructor with MindShare, Inc., where he has trained hundreds of engineers
Don Anderson is an expert on digital electronics and system design. He passes on his wealth of experience by training engineers, programmers, and technicians at MindShare, Inc.
Tom Shanley is President of MindShare, Inc.


Excerpts

Excerpts

The MindShare Architecture Series The MindShare Architecture book series currently includes the books listed below. The entire book series is published by Addison-Wesley. Books about Processor Architecture: 80486 System Architecture, Third Edition , 0-201-40994-1 Pentium Processor System Architecture, Second Edition , 0-201-40992-5 Pentium Pro and Pentium II System Architecture, Second Edition , 0-201-30973-4 Power PC System Architecture , 0-201-40990-9 Books About Bus Architecture: PCI System Architecture, Fourth Edition , 0-201-30974-2 PCI-X System Architecture , 0-201-72682-3 EISA System Architecture , 0-201-40995-X--Out-of-print Firewire System Architecture, Second Edition: IEEE 1394a , 0-201-48535-4 ISA System Architecture, Third Edition , 0-201-40996-8 Universal Serial Bus System Architecture 2.0 , 0-201-46137-4 HyperTransport™ System Architecture , 0-321-16845-3 PCI Express System Architecture , 0-321-15630-7 Books About Network Architecture: Network Architecture Infiniband Network Architecture , 0-321-11765-4 Books About Other Architectures: PCMCIA System Architecture, Second Edition: 16-Bit PC Cards , 0-201-40991-7 CardBus System Architecture , 0-201-40997-6 Plug and Play System Architecture , 0-201-41013-3 Protected Mode Software Architecture , 0-201-55447-X AGP System Architecture , 0-201-37964-3 Cautionary Note The reader should keep in mind that MindShare's book series often details rapidly evolving technologies, as is the case with PCI Express. This being the case, it should be recognized that the book is a "snapshot" of the state of the technology at the time the book was completed. We make every attempt to produce our books on a timely basis, but the next revision of the specification is not introduced in time to make necessary changes. This PCI Express book complies with revision 1.0a of the PCI Express™ Base Specification released and trademarked by the PCI Special Interest Group. Several expansion card form-factor specifications are planned for PCI Express, but only the Electro-mechanical specification, revision 1.0 was released when this book was completed. However, the chapter covering the Card Electromechanical topic reviews several form-factors that were under development at the time of writing. Intended Audience This book is intended for use by hardware and software design and support personnel. The tutorial approach taken may also make it useful to technical personnel not directly involved design, verification, and other support functions. Prerequisite Knowledge It is recommended that the reader has a reasonable background in PC architecture, including experience or knowledge of an I/O bus and related protocol. Because PCI Express maintains several levels of compatibility with the original PCI design, critical background information regarding PCI has been incorporated into this book. However, the reader may find it beneficial to read the MindShare publication entitled PCI System Architecture , which focusses on and details the PCI architecture. Topics and Organization Topics covered in this book and the flow of the book are as follows: Part 1: Background and Comprehensive Overview. Provides an architectural perspective of the PCI Express technology by comparing and contrasting it with the PCI and PCI-X buses. It also introduces the major features of the PCI Express architecture. Part 2: PCI Express Transaction Protocol. Includes packet format and field definition and use, along with transaction and link layer functions. Part 3: Physical Layer Description. Describes the physical layer functions, link training and initialization, reset, and electrical signaling. Part 4: Power-Related Topics. Discusses Power Budgeting and Power Management. Part 5: Optional Topics. Discusses the major features of PCI Express that are optional, including Hot Plug and Expansion Card implementation details. Part 6: PCI Express Configuration. Discusses the configuration process, accessing configuration space, and details the content and use of all configuration registers. Appendix: Test, Debug, and Verification Markets & Applications for the PCI Express™ Architecture Implementing Intelligent Adapters and Multi-Host Systems With PCI Express™ Technology PCI Express Class Codes Legacy Support for Locking Documentation Conventions This section defines the typographical convention used throughout this book. PCI Express™ PCI Express™ is a trademark of the PCI SIG. This book takes the liberty of abbreviating PCI Express as "PCI-XP" primarily in illustration where limited space is an issue. Hexadecimal Notation All hex numbers are followed by a lower case "h." For example: 89F2BD02h 0111h Binary Notation All binary numbers are followed by a lower case "b." For example: 1000 1001 1111 0010b 01b Decimal Notation Number without any suffix are decimal. When required for clarity, decimal numbers are followed by a lower case "d." Examples: 9 15 512d Bits Versus Bytes Notation This book represents bit with lower case "b" and bytes with an upper case "B." For example: Megabits/second = Mb/s Megabytes/second = MB/s Bit Fields Groups bits are represented with the high-order bits first followed by the loworder bits and enclosed by brackets. For example: 7:0 = bits 0 through 7 Active Signal States Signals that are active low are followed by #, as in PERST# and WAKE#. Active high signals have no suffix, such as POWERGOOD. Visit Our Web Site Our web site lists all of our courses and the delivery options available for each course: Information on MindShare courses: Self-paced DVDs and CDs Live web-delivered classes Live on-site classes. Free short courses on selected topics Technical papers Errata for a number of our books All of our books are listed and can be ordered in bound or e-book versions. www.mindshare.com We Want Your Feedback MindShare values you comments and suggestions. Contact us at: Phone: (719) 487-1417 or within the U.S. (800) 633-1440 Fax: (719) 487-1434 (Fax) Technical seminars: E-mail nancy@mindshare.com Technical questions: E-mail don@mindshare.com or tom@mindshare.com General information: E-mail info@mindshare.com Mailing Address: MindShare, Inc. 4285 Slash Pine Drive Colorado Springs, CO 80908 0321156307P08262003 Excerpted from PCI Express System Architecture by Ravi Budruk, Don Anderson, Tom Shanley, MindShare, Inc. Staff, Solari All rights reserved by the original copyright owners. Excerpts are provided for display purposes only and may not be reproduced, reprinted or distributed without the written permission of the publisher.

Table of Contents

About This Book
The MindShare Architecture Seriesp. 1
Cautionary Notep. 2
Intended Audiencep. 2
Prerequisite Knowledgep. 3
Topics and Organizationp. 3
Documentation Conventionsp. 4
PCI Expressp. 4
Hexadecimal Notationp. 4
Binary Notationp. 4
Decimal Notationp. 4
Bits Versus Bytes Notationp. 5
Bit Fieldsp. 5
Active Signal Statesp. 5
Visit Our Web Sitep. 5
We Want Your Feedbackp. 6
Part 1 The Big Picture
Chapter 1 Architectural Perspective
Introduction To PCI Expressp. 9
Predecessor Buses Comparedp. 11
I/O Bus Architecture Perspectivep. 16
The PCI Express Wayp. 41
PCI Express Specificationsp. 54
Chapter 2 Architecture Overview
Introduction to PCI Express Transactionsp. 55
PCI Express Device Layersp. 69
Example of a Non-Posted Memory Read Transactionp. 96
Hot Plugp. 101
PCI Express Performance and Data Transfer Efficiencyp. 101
Part 2 Transaction Protocol
Chapter 3 Address Spaces & Transaction Routing
Introductionp. 106
Two Types of Local Link Trafficp. 108
Transaction Layer Packet Routing Basicsp. 113
Applying Routing Mechanismsp. 121
Plug-And-Play Configuration of Routing Optionsp. 135
Chapter 4 Packet-Based Transactions
Introduction to the Packet-Based Protocolp. 154
Transaction Layer Packetsp. 156
Data Link Layer Packetsp. 198
Chapter 5 ACK/NAK Protocol
Reliable Transport of TLPs Across Each Linkp. 210
Elements of the ACK/NAK Protocolp. 212
ACK/NAK DLLP Formatp. 219
ACK/NAK Protocol Detailsp. 220
Error Situations Reliably Handled by ACK/NAK Protocolp. 239
ACK/NAK Protocol Summaryp. 241
Recommended Priority To Schedule Packetsp. 244
Some More Examplesp. 244
Switch Cut-Through Modep. 248
Chapter 6 QoS/TCs/VCs and Arbitration
Quality of Servicep. 252
Perspective on QOS/TC/VC and Arbitrationp. 255
Traffic Classes and Virtual Channelsp. 256
Arbitrationp. 263
Chapter 7 Flow Control
Flow Control Conceptp. 286
Flow Control Buffersp. 288
Introduction to the Flow Control Mechanismp. 290
Flow Control Packetsp. 293
Operation of the Flow Control Model - An Examplep. 294
Infinite Flow Control Advertisementp. 301
The Minimum Flow Control Advertisementp. 303
Flow Control Initializationp. 304
Flow Control Updates Following FC_INITp. 308
Chapter 8 Transaction Ordering
Introductionp. 316
Producer/Consumer Modelp. 317
Native PCI Express Ordering Rulesp. 318
Relaxed Orderingp. 319
Modified Ordering Rules Improve Performancep. 322
Support for PCI Buses and Deadlock Avoidancep. 326
Chapter 9 Interrupts
Two Methods of Interrupt Deliveryp. 330
Message Signaled Interruptsp. 331
Legacy PCI Interrupt Deliveryp. 342
Devices May Support Both MSI and Legacy Interruptsp. 352
Special Consideration for Base System Peripheralsp. 353
Chapter 10 Error Detection and Handling
Backgroundp. 356
Introduction to PCI Express Error Managementp. 356
Sources of PCI Express Errorsp. 361
Error Classificationsp. 368
How Errors are Reportedp. 370
Baseline Error Detection and Handlingp. 372
Advanced Error Reporting Mechanismsp. 382
Summary of Error Logging and Reportingp. 392
Part 3 The Physical Layer
Chapter 11 Physical Layer Logic
Physical Layer Overviewp. 397
Transmit Logic Detailsp. 403
Receive Logic Detailsp. 437
Physical Layer Error Handlingp. 450
Chapter 12 Electrical Physical Layer
Electrical Physical Layer Overviewp. 453
High Speed Electrical Signalingp. 455
LVDS Eye Diagramp. 470
Transmitter Driver Characteristicsp. 477
Input Receiver Characteristicsp. 480
Electrical Physical Layer State in Power Statesp. 481
Chapter 13 System Reset
Two Categories of System Resetp. 487
Reset Exitp. 496
Link Wakeup from L2 Low Power Statep. 497
Chapter 14 Link Initialization & Training
Link Initialization and Training Overviewp. 500
Ordered-Sets Used During Link Training and Initializationp. 504
Link Training and Status State Machine (LTSSM)p. 508
Detailed Description of LTSSM Statesp. 513
LTSSM Related Configuration Registersp. 549
Part 4 Power-Related Topics
Chapter 15 Power Budgeting
Introduction to Power Budgetingp. 557
The Power Budgeting Elementsp. 558
Slot Power Limit Controlp. 562
The Power Budget Capabilities Register Setp. 564
Chapter 16 Power Management
Introductionp. 568
Primer on Configuration Softwarep. 569
Function Power Managementp. 585
Introduction to Link Power Managementp. 606
Link Active State Power Managementp. 608
Software Initiated Link Power Managementp. 629
Link Wake Protocol and PME Generationp. 638
Part 5 Optional Topics
Chapter 17 Hot Plug
Backgroundp. 650
Hot Plug in the PCI Express Environmentp. 651
Elements Required to Support Hot Plugp. 655
Card Removal and Insertion Proceduresp. 658
Standardized Usage Modelp. 663
Standard Hot Plug Controller Signaling Interfacep. 668
The Hot-Plug Controller Programming Interfacep. 670
Slot Numberingp. 681
Quiescing Card and Driverp. 681
The Primitivesp. 682
Chapter 18 Add-in Cards and Connectors
Introductionp. 686
Form Factors Under Developmentp. 703
Part 6 PCI Express Configuration
Chapter 19 Configuration Overview
Definition of Device and Functionp. 712
Definition of Primary and Secondary Busp. 714
Topology Is Unknown At Startupp. 714
Each Function Implements a Set of Configuration Registersp. 715
Host/PCI Bridge's Configuration Registersp. 716
Configuration Transactions Are Originated by the Processorp. 718
Configuration Transactions Are Routed Via Bus, Device, and Function Numberp. 718
How a Function Is Discoveredp. 719
How To Differentiate a PCI-to-PCI Bridge From a Non-Bridge Functionp. 719
Chapter 20 Configuration Mechanisms
Introductionp. 722
PCI-Compatible Configuration Mechanismp. 723
PCI Express Enhanced Configuration Mechanismp. 731
Type 0 Configuration Requestp. 732
Type 1 Configuration Requestp. 733
Example PCI-Compatible Configuration Accessp. 735
Example Enhanced Configuration Accessp. 736
Initial Configuration Accessesp. 738
Chapter 21 PCI Express Enumeration
Introductionp. 741
Enumerating a System With a Single Root Complexp. 742
Enumerating a System With Multiple Root Complexesp. 753
A Multifunction Device Within a Root Complex or a Switchp. 758
An Endpoint Embedded in a Switch or Root Complexp. 761
Memorize Your Identityp. 763
Root Complex Register Blocks (RCRBs)p. 765
Miscellaneous Rulesp. 766
Chapter 22 PCI Compatible Configuration Registers
Header Type 0p. 770
Header Type 1p. 802
PCI-Compatible Capabilitiesp. 845
Chapter 23 Expansion ROMs
ROM Purpose--Device Can Be Used In Boot Processp. 872
ROM Detectionp. 872
ROM Shadowing Requiredp. 875
ROM Contentp. 875
Execution of Initialization Codep. 885
Introduction to Open Firmwarep. 888
Chapter 24 Express-Specific Configuration Registers
Introductionp. 894
PCI Express Capability Register Setp. 896
PCI Express Extended Capabilitiesp. 929
RCRBp. 957
Appendices
Appendix A Test, Debug and Verificationp. 963
Appendix B Markets & Applications for the PCI Express Architecturep. 989
Appendix C Implementing Intelligent Adapters and Multi-Host Systems With PCI Express Technologyp. 999
Appendix D Class Codesp. 1019
Appendix E Locked Transactions Seriesp. 1033
Indexp. 1043
Go to:Top of Page