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Cover image for High-speed digital system design : a handbook of interconnect theory and design practices
Title:
High-speed digital system design : a handbook of interconnect theory and design practices
Personal Author:
Publication Information:
New York, N.Y. : John Wiley & Sons, 2000
ISBN:
9780471360902

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30000010046919 TK7888.3 H344 2000 Open Access Book Book
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Summary

Summary

A cutting-edge guide to the theory and practice of high-speed digital system design

An understanding of high-speed interconnect phenomena is essential for digital designers who must deal with the challenges posed by the ever-increasing operating speeds of today's microprocessors. This book provides a much-needed, practical guide to the state of the art of modern digital system design, combining easily accessible explanations with immensely useful problem-solving strategies. Written by three leading Intel engineers, High-Speed Digital System Design clarifies difficult and often neglected topics involving the effects of high frequencies on digital buses and presents a variety of proven techniques and application examples. Extensive appendices, formulas, modeling techniques as well as hundreds of figures are also provided.
Coverage includes:
* A thorough introduction to the digital aspects of basic transmission line theory
* Crosstalk and nonideal transmission line effects on signal quality and timings
* The impact of packages, vias, and connectors on signal integrity
* The effects of nonideal return current paths, high frequency power delivery, and simultaneous switching noise
* Explanations of how driving circuit characteristics affect the quality of the digital signal
* Digital timing analysis at the system level that incorporates high-speed signaling effects into timing budgets
* Methodologies for designing high-speed buses and handling the very large number of variables that affect interconnect performance
* Radiated emission problems and how to minimize system noise
* The practical aspects of making measurements in high-speed digital systems


Author Notes

Stephen H. Hall is a Senior Design Engineer at Intel Corporation, Portland, Oregon
Garrett W. Hall is a Silicon Systems Engineer at Intel Corporation
James A. McCall is a Senior Design Engineer at Intel Corporation


Reviews 1

Choice Review

Hall, Hall, and McCall, all from Intel Corporation, offer an excellent guidebook for interconnect design. They bring a wealth of practical experience to this book, and their writing is exceptionally clear and intuitive. The book is intentionally brief in the area of theory, and it does not contain many complex equations; chapter introductions are outstanding and provide insight. The book easily transitions from detailed component-level material (e.g., choosing a decoupling capacitor in a power delivery system) to broader design concepts (e.g., enclosure considerations and bus topologies). The 11 chapters and six appendixes span topics relating to printed circuit board design, connectors, timing analysis, overall design optimization, and even high-speed measurement techniques. Appendixes cover topics from very basic (e.g., definition of the decibel) to applied (e.g., FCC emission limits). Since this book covers material not typically part of college courses, it would not be considered a textbook. Instead, this very valuable work is highly recommended for design engineers and recent graduates struggling to transition from theory to real-world design. Professional level. M. S. Roden; California State University, Los Angeles


Table of Contents

Prefacep. xi
1. The Importance of Interconnect Designp. 1
1.1 The Basicsp. 2
1.2 The Past and the Futurep. 4
2. Ideal Transmission Line Fundamentalsp. 7
2.1 Transmission Line Structures on a PCB or MCMp. 7
2.2 Wave Propagationp. 8
2.3 Transmission Line Parametersp. 9
2.3.1 Characteristic Impedancep. 11
2.3.2 Propagation Velocity, Time, and Distancep. 14
2.3.3 Equivalent Circuit Models for SPICE Simulationp. 15
2.4 Launching Initial Wave and Transmission Line Reflectionsp. 18
2.4.1 Initial Wavep. 18
2.4.2 Multiple Reflectionsp. 19
2.4.3 Effect of Rise Time on Reflectionsp. 26
2.4.4 Reflections From Reactive Loadsp. 28
2.4.5 Termination Schemes to Eliminate Reflectionsp. 32
2.5 Additional Examplesp. 36
2.5.1 Problemp. 36
2.5.2 Goalsp. 36
2.5.3 Calculating the Cross-Sectional Geometry of the PCBp. 37
2.5.4 Calculating the Propagation Delayp. 38
2.5.5 Determining the Wave Shape Seen at the Receiverp. 39
2.5.6 Creating an Equivalent Circuitp. 40
3. Crosstalkp. 42
3.1 Mutual Inductance and Mutual Capacitancep. 42
3.2 Inductance and Capacitance Matrixp. 43
3.3 Field Simulatorsp. 45
3.4 Crosstalk-Induced Noisep. 45
3.5 Simulating Crosstalk Using Equivalent Circuit Modelsp. 51
3.6 Crosstalk-Induced Flight Time and Signal Integrity Variationsp. 52
3.6.1 Effect of Switching Patterns on Transmission Line Performancep. 53
3.6.2 Simulating Traces in a Multiconductor System Using a Single-Line Equivalent Modelp. 59
3.7 Crosstalk Trendsp. 62
3.8 Termination of Odd- and Even-Mode Transmission Line Pairsp. 65
3.8.1 Pi Termination Networkp. 65
3.8.2 T Termination Networkp. 66
3.9 Minimization of Crosstalkp. 67
3.10 Additional Examplesp. 68
3.10.1 Problemp. 69
3.10.2 Goalsp. 70
3.10.3 Determining the Maximum Crosstalk-Induced Impedance and Velocity Swingp. 70
3.10.4 Determining if Crosstalk Will Induce False Triggersp. 72
4. Nonideal Interconnect Issuesp. 74
4.1 Transmission Line Lossesp. 74
4.1.1 Conductor DC Lossesp. 75
4.1.2 Dielectric DC Lossesp. 75
4.1.3 Skin Effectp. 76
4.1.4 Frequency-Dependent Dielectric Lossesp. 87
4.2 Variations in the Dielectric Constantp. 91
4.3 Serpentine Tracesp. 92
4.4 Intersymbol Interferencep. 95
4.5 Effects of 90[deg] Bendsp. 97
4.6 Effect of Topologyp. 99
5. Connectors, Packages, and Viasp. 102
5.1 Viasp. 102
5.2 Connectorsp. 104
5.2.1 Series Inductancep. 104
5.2.2 Shunt Capacitancep. 105
5.2.3 Connector Crosstalkp. 105
5.2.4 Effects of Inductively Coupled Connector Pin Fieldsp. 106
5.2.5 EMIp. 109
5.2.6 Connector Design Guidelinesp. 110
5.3 Chip Packagesp. 112
5.3.1 Common Types of Packagesp. 113
5.3.2 Creating a Package Modelp. 117
5.3.3 Effects of a Packagep. 121
5.3.4 Optimal Pin-Outsp. 127
6. Nonideal Return Paths, Simultaneous Switching Noise, and Power Deliveryp. 129
6.1 Nonideal Current Return Pathsp. 129
6.1.1 Path of Least Inductancep. 129
6.1.2 Signals Traversing a Ground Gapp. 130
6.1.3 Signals That Change Reference Planesp. 134
6.1.4 Signals Referenced to a Power or a Ground Planep. 135
6.1.5 Other Nonideal Return Path Scenariosp. 140
6.1.6 Differential Signalsp. 140
6.2 Local Power Delivery Networksp. 141
6.2.1 Determining the Local Decoupling Requirements for High-Speed I/Op. 144
6.2.2 System-Level Power Deliveryp. 147
6.2.3 Choosing a Decoupling Capacitorp. 149
6.2.4 Frequency Response of a Power Delivery Systemp. 150
6.3 SSO/SSNp. 151
6.3.1 Minimizing SSNp. 154
7. Buffer Modelingp. 156
7.1 Types of Modelsp. 157
7.2 Basic CMOS Output Bufferp. 157
7.2.1 Basic Operationp. 157
7.2.2 Linear Modeling of the CMOS Bufferp. 164
7.2.3 Behavioral Modeling of the Basic CMOS Bufferp. 172
7.3 Output Buffers That Operate in the Saturation Regionp. 175
7.4 Conclusionsp. 177
8. Digital Timing Analysisp. 178
8.1 Common-Clock Timingp. 178
8.1.1 Common-Clock Timing Equationsp. 180
8.2 Source Synchronous Timingp. 183
8.2.1 Source Synchronous Timing Equationsp. 186
8.2.2 Deriving Source Synchronous Timing Equations from an Eye Diagramp. 189
8.2.3 Alternative Source Synchronous Schemesp. 191
8.3 Alternative Bus Signaling Techniquesp. 192
8.3.1 Incident Clockingp. 192
8.3.2 Embedded Clockp. 192
9. Design Methodologiesp. 194
9.1 Timingsp. 195
9.1.1 Worst-Case Timing Spreadsheetp. 196
9.1.2 Statistical Spreadsheetsp. 198
9.2 Timing Metrics, Signal Quality Metrics, and Test Loadsp. 200
9.2.1 Voltage Reference Uncertaintyp. 200
9.2.2 Simulation Reference Loadsp. 202
9.2.3 Flight Timep. 206
9.2.4 Flight-Time Skewp. 207
9.2.5 Signal Integrityp. 209
9.3 Design Optimizationp. 210
9.3.1 Paper Analysisp. 211
9.3.2 Routing Studyp. 212
9.4 Sensitivity Analysisp. 215
9.4.1 Initial Trend and Significance Analysisp. 215
9.4.2 Ordered Parameter Sweepsp. 221
9.4.3 Phase 1 Solution Spacep. 224
9.4.4 Phase 2 Solution Spacep. 225
9.4.5 Phase 3 Solution Spacep. 228
9.5 Design Guidelinesp. 229
9.6 Extractionp. 230
9.7 General Rules of Thumb to Follow When Designing a Systemp. 230
10. Radiated Emissions Compliance and System Noise Minimizationp. 232
10.1 FCC Radiated Emission Specificationsp. 233
10.2 Physical Mechanisms of Radiationp. 233
10.2.1 Differential-Mode Radiationp. 234
10.2.2 Common-Mode Radiationp. 241
10.2.3 Wave Impedancep. 245
10.3 Decoupling and Chokingp. 246
10.3.1 High-Frequency Decoupling at the System Levelp. 248
10.3.2 Choking Cables and Localized Power and Ground Planesp. 253
10.3.3 Low-Frequency Decoupling and Ground Isolationp. 261
10.4 Additional PCB Design Criteria, Package Considerations, and Pin-Outsp. 263
10.4.1 Placement of High-Speed Components and Tracesp. 263
10.4.2 Crosstalkp. 263
10.4.3 Pin Assignments and Package Choicep. 264
10.5 Enclosure (Chassis) Considerationsp. 265
10.5.1 Shielding Basicsp. 265
10.5.2 Aperturesp. 267
10.5.3 Resonancesp. 272
10.6 Spread Spectrum Clockingp. 273
11. High-Speed Measurement Techniquesp. 276
11.1 Digital Oscilloscopesp. 276
11.1.1 Bandwidthp. 277
11.1.2 Samplingp. 278
11.1.3 Other Effectsp. 281
11.1.4 Statisticsp. 283
11.2 Time-Domain Reflectometryp. 283
11.2.1 TDR Theoryp. 284
11.2.2 Measurement Factorsp. 287
11.3 TDR Accuracyp. 289
11.3.1 Launch Parasiticsp. 290
11.3.2 Probe Typesp. 292
11.3.3 Reflectionsp. 293
11.3.4 Interface Transmission Lossp. 293
11.3.5 Cable Lossp. 294
11.3.6 Amplitude Offset Errorp. 294
11.4 Impedance Measurementp. 295
11.4.1 Accurate Characterization of Impedancep. 295
11.4.2 Measurement Region in TDR Impedance Profilep. 297
11.5 Odd- and Even-Mode Impedancep. 299
11.6 Crosstalk Noisep. 299
11.7 Propagation Velocityp. 300
11.7.1 Length Difference Methodp. 301
11.7.2 Y-Intercept Methodp. 301
11.7.3 TDT Methodp. 302
11.8 Vector Network Analyzerp. 303
11.8.1 Introduction to S Parametersp. 304
11.8.2 Equipmentp. 305
11.8.3 One-Port Measurements (Z[subscript o],L,C)p. 305
11.8.4 Two-Port Measurements (T[subscript d], Attenuation, Crosstalk)p. 310
11.8.5 Calibrationp. 314
11.8.6 Calibration for One-Port Measurementsp. 315
11.8.7 Calibration for Two-Port Measurementsp. 316
11.8.8 Calibration Verificationp. 316
Appendix A Alternative Characteristic Impedance Formulasp. 318
A.1 Microstripp. 318
A.2 Symmetric Striplinep. 319
A.3 Offset Striplinep. 319
Appendix B GTL Current-Mode Analysisp. 321
B.1 Basic GTL Operationp. 321
B.2 GTL Transitions When a Middle Agent Is Drivingp. 323
B.3 GTL Transitions When an End Agent With a Termination Is Drivingp. 325
B.4 Transitions When There is a Pull-Up at the Middle Agentp. 327
Appendix C Frequency-Domain Components in a Digital Signalp. 329
Appendix D Useful S-Parameter Conversionsp. 332
D.1 ABCD, Z, and Y Parametersp. 332
D.2 Normalizing the S Matrix to a Different Characteristic Impedancep. 335
D.3 Derivation of the Formulas Used to Extract the Mutual Inductance and Capacitance from a Short Structure Using S[subscript 21] Measurementsp. 336
D.4 Derivation of the Formula to Extract Skin Effect Resistance from a Transmission Linep. 337
Appendix E Definition of the Decibelp. 338
Appendix F FCC Emission Limitsp. 340
Bibliographyp. 342
Indexp. 345
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