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Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
|---|---|---|---|---|---|
Searching... | 30000010047110 | TK7895.M5 D47 2001 | Open Access Book | Book | Searching... |
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Summary
Summary
This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola.
Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth:
Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testabilityDesign of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.
Author Notes
About the Editors...
Anantha Chandrakasan is an associate professor of electrical engineering and computer science at the Massachusetts Institute of Technology. Dr. Chandrakasan has received numerous awards and has served on the technical program committees of various IEEE and ACM conferences. His research interests include the energy efficient implementation of DSPs, wireless microsensor networks, and CAD tools for VLSI.
William J. Bowhill is a principal member of technical staff in Compaq Computer Corporation's Alpha Development Group (formerly Digital Equipment Corp.). He has contributed to many VAX and Alpha microprocessor designs. Prior to joining Digital in 1985, he designed telecommunication chips for Standard Telecommunication Research Laboratories in England. He has a B.Eng. from Liverpool University.
Frank Fox (Thomas F. Fox) has been a vice president at Rambus Inc., since 1998. Previously, he worked for Digital Equipment Corporation, where he led the fifth generation Alpha microprocessor design team. During his fourteen years at Digital, he designed many microprocessors and consulted on CMOS technology and CAD tools. Dr. Fox has a B.E. from University College Cork, National University of Ireland and a Ph.D. from Trinity College, Dublin University.
Table of Contents
| Preface | p. xix |
| Part I Overview | p. 1 |
| Chapter 1 Impact of Physical Technology on Architecture | p. 3 |
| Part II Technology Issues | p. 25 |
| Chapter 2 CMOS Scaling and Issues in Sub-0.25 [mu]m Systems | p. 27 |
| Chapter 3 Techniques for Leakage Power Reduction | p. 46 |
| Chapter 4 Low-Voltage Technologies | p. 63 |
| Chapter 5 Soi Technology and Circuits | p. 80 |
| Chapter 6 Models of Process Variations in Device and Interconnect | p. 98 |
| Part III Circuit Styles for Logic | p. 117 |
| Chapter 7 Basic Logic Families | p. 119 |
| Chapter 8 Issues in Dynamic Logic Design | p. 140 |
| Chapter 9 Self-Timed Pipelines | p. 158 |
| Chapter 10 High-Speed VLSI Airthmetic Units: Adders and Multipliers | p. 181 |
| Part IV Clocking | p. 205 |
| Chapter 11 Clocked Storage Elements | p. 207 |
| Chapter 12 Design of High-Speed CMOS PLLs and DLLs | p. 235 |
| Chapter 13 Clock Distribution | p. 261 |
| Part V Memory System Design | p. 283 |
| Chapter 14 Register Files and Chahes | p. 285 |
| Chapter 15 Embedded Dram | p. 309 |
| Part VI Interconnect and I/O | p. 329 |
| Chapter 16 Analyzing on-Chip Interconnect Effects | p. 331 |
| Chapter 17 Techniques for Driving Interconnect | p. 352 |
| Chapter 18 I/O and ESD Circuit Design | p. 377 |
| Chapter 19 High-Speed Electrical Signaling | p. 397 |
| Part VII Reliability | p. 427 |
| Chapter 20 Electromigration Reliability | p. 429 |
| Chapter 21 Hot Carrier Reliability | p. 449 |
| Part VIII Cad Tools and Test | p. 467 |
| Chapter 22 Overview of Computer-Aided Design Tools | p. 469 |
| Chapter 23 Timing Verification | p. 480 |
| Chapter 24 Design and Analysis of Power Distribution Networks | p. 499 |
| Chapter 25 Testing of High-Performance Processors | p. 523 |
| Index | p. 545 |
