High-speed VLSI interconnections

This Second Edition focuses on emerging topics and advances in the field of VLSI interconnections

In the decade since High-Speed VLSI Interconnections was first published, several major developments have taken place in the field. Now, updated to reflect these advancements, this Second Edition includes new information on copper interconnections, nanotechnology circuit interconnects, electromigration in the copper interconnections, parasitic inductances, and RLC models for comprehensive analysis of interconnection delays and crosstalk.

Each chapter is designed to exist independently or as a part of one coherent unit, and several appropriate exercises are provided at the end of each chapter, challenging the reader to gain further insight into the contents being discussed. Chapter subjects include:
*

Preliminary Concepts
*

Parasitic Resistances, Capacitances, and Inductances
*

Interconnection Delays
*

Crosstalk Analysis
*

Electromigration-Induced Failure Analysis
*

Future Interconnections

High-Speed VLSI Interconnections, Second Edition is an indispensable reference for high-speed VLSI designers, RF circuit designers, and advanced students of electrical engineering.

Author Notes

AShok k. Goel, PhD, is Associate Professor of Electrical Engineering at Michigan Technological University. He is the author of more than thirty journal publications and numerous conference proceedings. His research interests include nanotechnology circuit design, high-speed VLSI interconnections, device physics and modeling, and semiconductor TCAD.

Preface

1 Preliminary Concepts and More

1.1 Interconnections for VLSI Applications

1.1.1 Metallic Interconnections - Multilevel, Multilayer and Multipath Configurations

1.1.2 Optical Interconnections

1.1.3 Superconducting Interconnections

1.2 Copper Interconnections

1.2.1 Advantages of Copper Interconnections

1.2.2 Challenges Posed by Copper Interconnections

1.2.3 Fabrication Processes for Copper Interconnections

1.2.4 Damascene Processing of Copper Interconnections

1.3 Method of Images

1.4 Method of Moments

1.5 Even and Odd Mode Capacitances

1.5.1 Two Coupled Conductors

1.5.2 Three Coupled Conductors

1.6 Transmission Line Equations

1.7 Miller's Theorem

1.8 Inverse Laplace Transformation

1.9 A Resistive Interconnection as a Ladder Network

1.9.1 Open Circuit Interconnection

1.9.2 Short Circuited Interconnection

1.9.3 Application of the Ladder Approximation to a Multipath Interconnection

1.10 Propagation Modes in a Microstrip Interconnection

1.11 Slow-Wave Mode Propagation

1.11.1 Quasi-TEM Analysis

1.11.2 Comparison with Experimental Results

1.12 Propagation Delays

Exercises

References

2 Parasitic Resistances, Capacitances and Inductances

2.1 Parasitic Resistances - General Considerations

2.2 Parasitic Capacitances - General Considerations

2.2.1 Parallel Plate Capacitance

2.2.2 Fringing Capacitances

2.2.3 Coupling Capacitances

2.3 Parasitic Inductances - General Considerations

2.3.1 Self and Mutual Inductances

2.3.2 Partial Inductances

2.3.3 Methods for Inductance Extraction

2.3.4 Effect of Inductances on Interconnection Delays

2.4 Approximate Formulas for Capacitances

2.4.1 Single Line on a Ground Plane

2.4.2 Two Lines on a Ground Plane

2.4.3 Three Lines on a Ground Plane

2.4.4 Single Plate with Finite Dimensions on a Ground Plane

2.5 The Green's Function Method - Using Method of Images

2.5.1 Green's Function Matrix for Interconnections Printed on the Substrate

2.5.2 Green's Function Matrix for Interconnections Embedded in the Substrate

2.5.3 Application of the Method of Moments

2.5.4 Even and Odd Mode Capacitances

2.5.5 Ground and Coupling Capacitances

2.5.6 The Program IPCSGV

2.5.7 Parametric Dependence of Interconnection Capacitances

2.6 The Green's Function Method - Fourier Integral Approach

2.6.1 Green's Function for Multilevel Interconnections

2.6.2 Multiconductor Interconnection Capacitances

2.6.3 Piecewise Linear Charge Distribution Function

2.6.4 Calculation of Interconnection Capacitances

2.7 The Network Analogue Method

2.7.1 Representation of Subregions by Network Analogues

2.7.2 Diagonalized System for Single Level Interconnections

2.7.3 Diagonalized System for Multilevel Interconnections

2.7.4 Interconnection Capacitances and Inductances

2.7.5 The Program "ICIMPGV"

2.7.6 Parametric Dependence of Interconnection Capacitances

2.7.7 Parametric Dependence of Interconnection Inductances

2.8 Simplified Formulas for Interconnection Capacitances and Inductances on Silicon and GaAs Substrates

2.8.1 Line Capacitances and Inductances

2.8.2 Coupling Capacitances and Inductances

2.9 Inductance Extraction Using FastHenry

2.9.1 The Program "FastHenry"

2.9.2 Extraction Results Using FastHenry

2.10 Copper Interconnections - Resistance Modeling

2.10.1 Effect of Surface/Interface Scattering on the Interconnection Resistivity

2.10.2 Effect of Diffusion Barrier on the Interconnection Resistivity

2.11 Electrode Capacitances in a GaAs MESFET - An

Available:*

On Order

Summary

Summary

Author Notes

Table of Contents