Radio frequency system architecture and design

Communication devices such as smart phones, GPS systems, and Bluetooth, are now part of our daily lives more than ever before. This resource describes practical aspects of radio frequency communications systems design, bridging the gap between system-level design considerations and circuit-level design specifications.

Author Notes

John W. M. Rogers holds a Ph.D. in electrical engineering from Carleton University.

Mr. Rogers is an assistant professor in the Department of Electronics at Carleton University, Ottawa, Canada and a member of the Professional Engineers of Ontario.

050

Preface	p. xi
Chapter 1 Introduction to RF Systems Design	p. 1
1.1 Introduction	p. 1
1.2 What is a Radio and Why Do We Need One?	p. 1
1.3 The Radio Spectrum	p. 2
1.4 A Communication Device	p. 3
1.5 Baseband Signal Processing Versus RFIC Design	p. 6
1.6 Overview	p. 7
References	p. 8
Chapter 2 An introduction to Communication Systems	p. 9
2.1 A Simple Digital Communication System	p. 10
2.2 Basic Modulation Schemes	p. 12
2.2.1 Amplitude Shift Keying (ASK)	p. 12
2.2.2 Phase Shift Keying (PSK)	p. 13
2.2.3 Frequency Shift Keying (FSK)	p. 15
2.2.4 Quadrature Amplitude Modulation (QAM)	p. 16
2.3 Signal Models	p. 16
2.3.1 Complex Lowpass Equivalent Signal Representation	p. 16
2.3.2 Signal Space Diagrams	p. 17
2.4 System Model	p. 24
2.4.1 Symbol Map	p. 25
2.4.2 Pulse Shaping Filter	p. 25
2.4.3 Modulator	p. 26
2.4.4 Additive White Gaussian Noise (AWGN) Channel Model	p. 26
2.4.5 Demodulator	p. 27
2.4.6 Receive Filter	p. 27
2.4.7 Signal Sampling	p. 28
2.4.8 Decision Device	p. 29
2.5 Probability of Error Analysis	p. 31
2.5.1 Binary Signaling	p. 31
2.5.2 M-ary Signaling	p. 36
2.5.3 BER Comparison of Different Modulation Schemes	p. 39
2.6 Signal Spectral Density	p. 42
2.6.1 Signal Bandwidth	p. 44
2.6.2 Pulse Shaping and Intersymbol Interference	p. 45
2.6.3 Frequency Division Multiple Access	p. 51
2.7 Wireless Channel Models	p. 53
2.7.1 Signal Attenuation	p. 53
2.7.2 Propagation Delay	p. 56
2.7.3 Multipath Interference and Fading	p. 59
2.8 Advanced Communication Techniques	p. 63
2.8.1 Orthogonal Frequency Division Multiplexing	p. 63
2.8.2 Multiple Antenna Systems	p. 68
2.8.3 Spread Spectrum Systems	p. 71
2.8.4 Error Control Coding	p. 73
2.9 Summary	p. 76
References	p. 77
Chapter 3 Basic RF Design Concepts and Building Blocks	p. 79
3.1 Introduction	p. 79
3.2 Gain	p. 79
3.3 Noise	p. 80
3.3.1 Thermal Noise	p. 80
3.3.2 Available Noise Power	p. 81
3.3.3 Available Noise Power from an Antenna	p. 82
3.3.4 The Concept of Noise Figure	p. 83
3.3.5 Phase Noise	p. 86
3.4 Linearity and Distortion in RF Circuits	p. 89
3.4.1 Power Series Expansion	p. 89
3.4.2 Third-Order Intercept Point	p. 94
3.4.3 Second-Order Intercept Point	p. 96
3.4.4 Fifth-Order Intercept Point	p. 97
3.4.5 The 1-dB Compression Point	p. 97
3.4.6 Relationships Between 1-dB Compression and IP3 Points	p. 99
3.4.7 Broadband Measures of Linearity	p. 100
3.4.8 Nonlinearity with Feedback	p. 102
3.4.9 Nonlinear Systems with Memory: Volterra Series	p. 105
3.5 Basic RF Building Blocks	p. 118
3.5.1 Low Noise Amplifiers (LNAs)	p. 119
3.5.2 Mixers	p. 119
3.5.3 Filters	p. 121
3.5.4 Voltage-Controlled Oscillators and Frequency Synthesizers	p. 122
3.5.5 Variable Gain Amplifiers	p. 122
3.5.6 Power Amplifiers	p. 122
3.5.7 Phase Shifters	p. 124
3.5.8 Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters	p. 126
3.5.9 RF Switch	p. 126
3.5.10 Antenna	p. 126
References	p. 126
Chapter 4 System-Level Architecture	p. 129
4.1 Introduction	p. 129
4.2 Superheterodyne Transceivers	p. 129
4.3 Direct Conversion Transceivers	p. 133
4.4 Offset Phase Locked Loop (PLL) Transmitters	p. 135
4.5 Low IF Transceiver	p. 136
4.6 Sliding IF Transceiver	p. 142
4.7 An Upconversion-Downconversion Receiver Architecture	p. 143
4.8 Coherent Versus Noncoherent Receivers	p. 144
4.9 Image Rejecting/Sideband Suppression Architectures	p. 145
4.10 An Alternative Single-Sideband Mixer	p. 147
4.11 Image Rejection with Amplitude and Phase Mismatch	p. 147
4.12 LO Generation	p. 149
4.13 Channel Selection at RF	p. 152
4.14 Transmitter Linearity Techniques	p. 153
4.15 Multiple-Input Multiple-Output (MIMO) Radio Architectures	p. 155
References	p. 157
Chapter 5 System-Level Design Considerations	p. 159
5.1 Introduction	p. 159
5.2 The Noise Figure of Components in Series	p. 159
5.3 The Linearity of Components in Series	p. 163
5.4 Dynamic Range	p. 165
5.5 Image Signals and Image Reject Filtering	p. 166
5.6 Blockers and Blocker Filtering	p. 171
5.7 The Effect of Phase Noise and LO Spurs on SNR in a Receiver	p. 175
5.8 DC Offset	p. 176
5.9 Second-Order Nonlinearity Issues	p. 177
5.10 Automatic Gain Control Issues	p. 178
5.11 Frequency Planning Issues	p. 179
5.11.1 Dealing with Spurs in Frequency Planning	p. 181
5.12 EVM in Transmitters Including Phase Noise, Linearity, IQ Mismatch, EVM with OFDM Waveforms, and Nonlinearity	p. 187
5.13 Adjacent Channel Power	p. 196
5.14 Important Considerations in Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC)	p. 199
5.15 ADC and DAC Basics	p. 200
References	p. 206
Chapter 6 Frequency Synthesis	p. 207
6.1 Introduction	p. 207
6.2 Integer-N PLL Synthesizers	p. 207
6.3 PLL Components	p. 209
6.3.1 Voltage-Controlled Oscillators (VCOs) and Dividers	p. 209
6.3.2 Phase Detectors	p. 210
6.3.3 The Loop Filter	p. 214
6.4 Continuous-Time Analysis for PLL Synthesizers	p. 215
6.4.1 Simplified Loop Equations	p. 215
6.4.2 PLL System Frequency Response and Bandwidth	p. 218
6.4.3 Complete Loop Transfer Function Including C 2	p. 219
6.5 Discrete Time Analysis for PLL Synthesizers	p. 220
6.6 Transient Behavior of PLLs	p. 222
6.6.1 PLL Linear Transient Behavior	p. 223
6.6.2 Nonlinear Transient Behavior	p. 226
6.6.3 Various Noise Sources in PLL Synthesizers	p. 232
6.6.4 In-Band and Out-of-Band Phase Noise in PLL Synthesis	p. 235
6.7 Reference Feedthrough	p. 239
6.8 Fractional-N Frequency Synthesizers	p. 242
6.8.1 Fractional-N Synthesizer with Dual Modulus Prescaler	p. 243
6.8.2 Fractional-N Synthesizer with Multimodulus Divider	p. 245
6.8.3 Fractional-N Spurious Components	p. 246
6.9 All-Digital Phase Locked Loops	p. 248
6.9.1 The Evolution to a More Digital Architecture	p. 249
6.9.2 Phase Noise Limits Due to TDC Resolution	p. 250
6.9.3 Phase Noise Limits Due to DCO Resolution	p. 251
6.9.4 Time to Digital Converter Architecture	p. 251
6.9.5 The Digital Loop Filter	p. 254
6.9.6 ADPLL Noise Calculations	p. 259
6.9.7 Time to Digital Converter Circuits	p. 260
References	p. 262
Chapter 7 Block-Level Radio Design Examples	p. 267
7.1 An IEEE 802.11n Transceiver for the 5-GHz Band	p. 267
7.1.1 Baseband Signal Processing	p. 267
7.1.2 RF Considerations	p. 271
7.2 A Basic GPS Receiver Design	p. 281
7.2.1 GPS Overview	p. 281
7.2.2 RF Specification Calculations	p. 284
References	p. 287
About the Authors	p. 289
Index	p. 291

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