Design and test of digital circuits by quantum-dot cellular automata

Title:

Publication Information:

Boston, MA : Artech House Publishers, 2008

ISBN:

9781596932678

Subject Term:

Quantum dots

Digital electronics -- Design and construction

Digital electronics -- Testing

Nanoelectronics

Added Author:

Lombardi, Fabrizio, 1955-

Huang, Jing, 1970-

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Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010163801	TK7874.88 D47 2008	Open Access Book	Book	Searching... Unknown

Probing both the science and the engineering involved, this one-of-a-kind resource reviews current microchip fabrication methods and architectures and discusses fundamentals of nanoscale design and DNA self-assembly. Moreover, the book surveys current limitations and challenges, and features detailed case studies of lightweight self-organizing computer architectures. This roadmap to DNA microchip synthesis is essential reading for all engineers and researchers involved in developing nanoscale computer structures, devices, and applications.

Preface	p. xiii
Chapter 1 Introduction	p. 1
1.1 Challenges	p. 2
1.2 Previous Work	p. 3
1.3 Contributions	p. 4
1.4 Book Outline	p. 7
References	p. 8
Chapter 2 Nano Devices and Architectures Overview	p. 11
2.1 Nanoelectronic Devices	p. 12
2.1.1 Carbon Nanotube-based Devices	p. 12
2.1.2 Nanowires	p. 14
2.1.3 Molecular Electronic Devices	p. 15
2.1.4 Single-Electron Devices	p. 17
2.1.5 Resonant Tunneling Diodes	p. 21
2.1.6 Spin Transistors	p. 22
2.2 Nano-scale Crossbars	p. 23
2.3 Architectures	p. 25
2.3.1 SET Architecture	p. 26
2.3.2 RTD Architecture	p. 26
2.3.3 NanoFabrics Architecture	p. 27
2.3.4 NanoPLA	p. 29
References	p. 33
Chapter 3 QCA	p. 37
3.1 QCA Implementation	p. 42
3.1.1 Metal QCA	p. 42
3.1.2 Molecular QCA	p. 44
3.1.3 Magnetic QCA	p. 45
3.2 Clocking	p. 45
3.3 Molecular Attachment	p. 49
3.4 Power Gain and Dissipation	p. 51
3.5 QCA Simulators	p. 53
3.5.1 QCADesigner	p. 54
3.6 QCA Circuits	p. 56
3.7 Comparison of Nanotechnology Devices	p. 61
References	p. 54
Chapter 4 QCA Combinational Logic Design	p. 69
4.1 Gate-based Combinational Logic Design	p. 69
4.1.1 Gate-based Design of QCA with Existing Commercial Synthesis Tools	p. 71
4.2 Logic Synthesis	p. 73
4.2.1 And/Or-based Logic Synthesis	p. 73
4.2.2 Muroga's MV-based Logic Synthesis	p. 75
4.2.3 MAjority Logic Synthesizer (MALS)	p. 75
4.3 Structural Design	p. 75
4.4 And-Or-Inverter (AOI) Gate	p. 76
4.4.1 AOI Gate Characterization	p. 76
4.4.2 Defect Characterization of the AOI Gate	p. 78
4.4.3 Logic Synthesis Using the AOI Gate	p. 82
4.4.4 Conclusion	p. 87
References	p. 89
Chapter 5 Logic-Level Testing and Defect Characterization	p. 91
5.1 Logic-Level Testing	p. 91
5.1.1 Stuck-at Test Properties of MV-based Circuits	p. 92
5.1.2 Test Set for MVs	p. 95
5.1.3 C-Testability of MV-based Designs	p. 96
5.2 Defect Characterization of Devices	p. 99
5.2.1 Simulation Engines	p. 101
5.2.2 MV Defect Analysis	p. 102
5.2.3 Interconnect Defect Analysis	p. 107
5.2.4 Probabilistic Analysis and Testing	p. 111
5.2.5 Defect Analysis and Testing of QCA Circuits	p. 116
5.2.6 Scaling in the Presence of Defects	p. 133
5.2.7 Conclusion	p. 140
References	p. 141
Chapter 6 Two-Dimensional Schemes for Clocking/Timing of QCA Circuits	p. 143
6.1 Clocking Analysis	p. 144
6.2 Two-Dimensional QCA Clocking	p. 146
6.3 Two-Dimensional Wave QCA Clocking	p. 151
6.4 Examples of QCA Circuits	p. 156
6.5 Feedback Paths	p. 159
6.6 Simulation Results	p. 160
6.6.1 2-to-1 Multiplexer	p. 161
6.6.2 One-bit Full Adder	p. 161
6.6.3 RS Flip-flop	p. 161
6.7 Conclusion	p. 162
References	p. 168
Chapter 7 Tile-Based QCA Design	p. 171
7.1 QCA Design by Tiling	p. 174
7.2 Fully Populated Grid Analysis	p. 176
7.3 Tiles Based on 3 X 3 Grids	p. 179
7.3.1 Orthogonal Tile	p. 179
7.3.2 Double Fan-out Tile	p. 183
7.3.3 Baseline Tile	p. 187
7.3.4 Fan-in Tile	p. 190
7.3.5 Triple Fan-out Tile	p. 192
7.4 Analysis of Results	p. 195
7.4.1 Configuration Selection	p. 196
7.5 Logic Analysis	p. 196
7.6 Examples of QCA Circuits	p. 200
7.6.1 One-bit Full Adder	p. 200
7.6.2 Parity Checker	p. 201
7.6.3 2-to-4 Decoder	p. 206
7.6.4 2-to-1 MUX	p. 208
7.7 Conclusion	p. 210
References	p. 211
Chapter 8 Sequential Circuit Design in QCA	p. 213
8.1 RS Flip-flop and D Flip-flop in QCA	p. 214
8.1.1 Defect Characterization of RS Flip-flop	p. 216
8.2 Timing Constraints in QCA Sequential Design	p. 219
8.2.1 Timing Constraints Using RS Flip-flops	p. 220
8.2.2 Timing Constraints using D Flip-flops	p. 221
8.3 Algorithm for Clocking Zone Assignment	p. 221
8.3.1 Algorithm Outline	p. 221
8.3.2 Algorithm Detail	p. 223
8.3.3 Algorithm for Coplanar Device	p. 226
8.3.4 Examples of QCA Circuits	p. 227
8.4 Defect Characterization of QCA Sequential Circuits	p. 229
8.5 Discussion and Conclusion	p. 239
References	p. 246
Chapter 9 QCA Memory	p. 247
9.1 Introduction	p. 247
9.2 Review of QCA Memories	p. 249
9.3 Parallel Memory Architecture	p. 252
9.3.1 Proposed Parallel QCA Memory Design	p. 252
9.3.2 Clocking Considerations	p. 255
9.3.3 Discussion and Comparison	p. 257
9.3.4 Simulations	p. 261
9.4 Serial Memory Architecture	p. 263
9.4.1 Memory Design by Tiling	p. 263
9.4.2 Clocking and Timing	p. 266
9.4.3 QCA Tiles	p. 268
9.4.4 Simulation	p. 271
9.4.5 Conclusion	p. 285
References	p. 285
Chapter 10 Implementing Universal Logic in QCA	p. 287
10.1 Universal Gate	p. 288
10.2 Universal Gate Designs	p. 289
10.2.1 And/Or-based Synthesis	p. 290
10.2.2 MV-based Synthesis	p. 290
10.3 Memory-based LUT	p. 294
10.4 Multiplexer-based LUT	p. 298
10.5 Discussion and Conclusion	p. 301
References	p. 302
Chapter 11 QCA Model for Computing and Energy Analysis	p. 305
11.1 Review on Reversible Computing	p. 306
11.2 Mechanical Model	p. 308
11.2.1 Model of QCA Cell	p. 309
11.2.2 Steady State Energy of QCA Devices	p. 312
11.3 Entropy and Dissipation Analysis	p. 315
11.3.1 Operation of the Mechanical Cell	p. 315
11.4 Landauer and Bennett Clocking Schemes	p. 320
11.5 Conclusion	p. 323
References	p. 325
Chapter 12 Fault Tolerance of Reversible QCA Circuits	p. 327
12.1 Hardware Redundancy Techniques	p. 328
12.2 Majority Multiplexing in QCA	p. 333
12.2.1 Fault Tolerant Capacity	p. 334
12.2.2 Restoration Speed of Multiplexing	p. 336
12.2.3 Summary	p. 338
12.3 Reversible Computing and Fault Tolerance	p. 339
12.4 Energy Dissipation of a Reversible MV Multiplexing System	p. 341
12.4.1 System Without Fault	p. 341
12.4.2 Dissipation in Fault Correction	p. 342
12.5 Conclusion	p. 344
References	p. 347
Chapter 13 Conclusion and Future Work	p. 349
App. A Preliminary for QCA Mechanical Model	p. 353
References	p. 356
App. B Validation of Mechanical Model	p. 357
B.1 Validation of Static Energy Analysis	p. 357
B.2 Validation of Dissipation Analysis	p. 358
References	p. 360
App. C Energy Dissipation Analysis of Circuit Units	p. 363
About the Authors	p. 367

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