Design & implementation (FPGA) of an all digital phase locked loop (ADPLL)

Select an Action

Title:

Personal Author:

Publication Information:

Skudai : Universiti Teknologi Malaysia, 2005

Physical Description:

xv, 99 p. : ill. ; 30 cm.

Subject Term:

DSP_DISSERTATION:

Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2005

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... FKE Library	FKE30000001671	TK7895.G36 K74 2005	Closed Access Thesis	UTM Project Paper (Closed Access)	Searching... Unknown
Searching... Perpustakaan Raja Zarith Sofiah	30000010096255	TK7895.G36 K74 2005	Closed Access Thesis	UTM Project Paper (Closed Access)	Searching... Unknown