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Cover image for Modern receiver front-ends: systems, circuits, and integration
Title:
Modern receiver front-ends: systems, circuits, and integration
Personal Author:
Publication Information:
Hoboken, N.J. : John Wiley & Sons, 2004
ISBN:
9780471225911

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Item Category 1
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30000010070430 TK7874.78 L37 2004 Open Access Book Book
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Summary

Summary

Architectures BABAK MATINPOUR and JOY LASKAR
* Describes the actual implementation of receiver architectures from the initial design to an IC-based product
* Presents many tricks-of-the-trade not usually covered in textbooks
* Covers a range of practical issues including semiconductor technology selection, cost versus performance, yield, packaging, prototype development, testing, and analysis
* Discusses architectures that are employed in modern broadband wireless systems


Author Notes

Sudipto Chakraborty is a senior research engineer in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, Georgia, where he is involved in analysis, design, and characterization of advanced wired and wireless circuits and systems towards advanced communication technologies using silicon-based processes.


Reviews 1

Choice Review

Laskar and Chakraborty (Georgia Tech) and Matinpour (Vermont Silicon, Inc.) outline the state of the art in radio frequency (RF) and microwave integrated circuit design for receivers used in wireless communication systems. They include material on system-level design, semiconductor electronic circuit design, packaging "tricks of the trade" in design, and practical considerations. They provide a good balance between theory, design, and practical issues in developing a fully integrated front end design for a wireless receiver. They assume readers have prerequisite backgrounds in electronic circuits, communication theory, and microwaves. Among the many topics addressed are comparisons and trade-offs in superheterodyne and direct conversion receiver architectures, image channel rejection, link budget analysis, linearity, multipath and fading communication channels, spatial diversity, coding, Gilbert cell mixer technologies, patch antenna design, orthogonal frequency division multiplexing (OFDM) high data rate wireless systems, system on a chip design, and future trends in wireless technology including RF CMCS cell phones and ultrawideband communication technology. The well-written text is illustrated with numerous references. No problems are included, which would have been beneficial for classroom adoption. For libraries associated with graduate academic programs in electrical engineering. ^BSumming Up: Recommended. Graduate students through professionals. F. A. Cassara Polytechnic University


Table of Contents

Prefacep. xi
Acknowledgmentsp. xiii
1 Introductionp. 1
1.1 Current State of the Artp. 3
2 Receiver System Designp. 7
2.1 Frequency Planningp. 7
2.1.1 Blockersp. 8
2.1.2 Spurs and Desensingp. 10
2.1.3 Transmitter Leakagep. 10
2.1.4 LO Leakage and Interferencep. 11
2.1.5 Imagep. 13
2.1.6 Half IFp. 13
2.2 Link Budget Analysisp. 14
2.2.1 Linearityp. 15
2.2.2 Noisep. 16
2.2.3 Signal-to-Noise Ratiop. 19
2.2.4 Receiver Gainp. 20
2.3 Propagation Effectsp. 21
2.3.1 Path Lossp. 22
2.3.2 Multipath and Fadingp. 23
2.3.3 Equalizationp. 24
2.3.4 Diversityp. 24
2.3.5 Codingp. 24
2.4 Interface Planningp. 25
2.5 Conclusionp. 25
3 Review of Receiver Architecturesp. 27
3.1 Heterodyne Receiversp. 28
3.2 Image Reject Receiversp. 30
3.2.1 Hartley Architecturep. 31
3.2.2 Weaver Architecturep. 32
3.3 Zero IF Receiversp. 32
3.4 Low IF Receiversp. 34
3.5 Issues in Direct Conversion Receiversp. 34
3.5.1 Noisep. 38
3.5.2 LO Leakage and Radiationp. 38
3.5.3 Phase and Amplitude Imbalancep. 38
3.5.4 DC Offsetp. 39
3.5.5 Intermodulationsp. 41
3.6 Architecture Comparison and Trade-offp. 43
3.7 Conclusionp. 43
4 Silicon-Based Receiver Designp. 47
4.1 Receiver Architecture and Designp. 48
4.1.1 System Description and Calculationsp. 48
4.1.2 Basics of OFDMp. 48
4.1.3 System Architecturesp. 50
4.1.4 System Calculationsp. 52
4.2 Circuit Designp. 54
4.2.1 SiGe BiCMOS Process Technologyp. 54
4.2.2 LNAp. 55
4.2.3 Mixerp. 57
4.2.4 Frequency Dividerp. 61
4.3 Receiver Design Stepsp. 61
4.3.1 Design and Integration of Building Blocksp. 62
4.3.2 DC Conditionsp. 62
4.3.3 Scattering Parametersp. 62
4.3.4 Small-Signal Performancep. 63
4.3.5 Transient Performancep. 64
4.3.6 Noise Performancep. 64
4.3.7 Linearity Performancep. 65
4.3.8 Parasitic Effectsp. 68
4.3.9 Process Variationp. 68
4.3.10 50-[Omega] and Non-50-[Omega] Receiversp. 68
4.4 Layout Considerationsp. 69
4.5 Characterization of Receiver Front-Endsp. 70
4.5.1 DC Testp. 71
4.5.2 Functionality Testp. 71
4.5.3 S-Parameter Testp. 71
4.5.4 Conversion Gain Testp. 73
4.5.5 Linearity Testp. 74
4.5.6 Noise Figure Testp. 74
4.5.7 I/Q Imbalancep. 74
4.5.8 DC Offsetp. 74
4.6 Measurement Results and Discussionsp. 76
4.6.1 Close Examination of Noise Figure and I/Q Imbalancep. 79
4.6.2 Comments on I/Q Imbalancep. 79
4.7 Conclusionp. 80
5 Subharmonic Receiver Designsp. 83
5.1 Illustration of Subharmonic Techniquesp. 84
5.2 Mixing Using Antisymmetric I--V Characteristicsp. 85
5.3 Impact of Mismatch Effectsp. 89
5.4 DC Offset Cancellation Mechanismsp. 92
5.4.1 Intrinsic DC Offset Cancellationp. 92
5.4.2 Extrinsic DC Offset Cancellationp. 93
5.5 Experimental Verification of DC Offsetp. 94
5.6 Waveform Shaping Before Mixingp. 98
5.6.1 Theory and Analysisp. 101
5.6.2 Experimental Verification on GaAs MESFET APDPp. 102
5.6.3 Implementation in Siliconp. 106
5.7 Design Steps for APDP-Based Receiversp. 109
5.8 Architectural Illustrationp. 111
5.9 Fully Monolithic Receiver Design Using Passive APDP Coresp. 112
5.9.1 Integrated Direct Conversion Receiver MMIC'sp. 112
5.9.2 Receiver Blocksp. 113
5.9.3 Additional Receiver Blocksp. 121
5.10 Reconfigurable Multiband Subharmonic Front-Endsp. 124
5.11 Conclusionp. 125
6 Active Subharmonic Receiver Designsp. 127
6.1 Stacking of Switching Coresp. 128
6.1.1 Description and Principlesp. 128
6.1.2 Subharmonic Receiver Architecturep. 131
6.2 Parallel Transistor Stacksp. 132
6.2.1 Active Mixerp. 132
6.2.2 Receiver Architecturep. 134
6.2.3 Extension to Passive Mixersp. 137
6.3 Extension to Higher-Order LO Subharmonicsp. 137
6.4 Multiple Phase Signal Generation from Oscillatorsp. 139
6.5 Future Direction and Conclusionp. 140
7 Design and Integration of Passive Componentsp. 143
7.1 System on Package (SoP)p. 144
7.1.1 Multilayer Bandpass Filterp. 146
7.1.2 Multilayer Balun Structurep. 148
7.1.3 Module-Integrable Antennawp. 149
7.1.4 Fully Integrated SoP Modulep. 149
7.2 On-Chip Inductorsp. 152
7.2.1 Inductor Modelingp. 153
7.2.2 Inductor Parametersp. 157
7.2.3 Application in Circuitsp. 158
7.3 Capacitorsp. 159
7.4 Differentially Driven Inductorsp. 163
7.5 Transformersp. 166
7.5.1 Electrical Parametersp. 166
7.5.2 Physical Constructionp. 168
7.5.3 Electrical Modelsp. 168
7.5.4 Frequency Response of Transformersp. 172
7.5.5 Step-Up/Step-Down Transformers and Circuit Applicationsp. 176
7.6 On-Chip Filtersp. 177
7.6.1 Filters Using Bond Wiresp. 179
7.6.2 Active Filtersp. 179
7.7 On-Wafer Antennasp. 185
7.8 Wafer-Level Packagingp. 187
7.9 Conclusionp. 188
8 Design for Integrationp. 191
8.1 System Design Considerationsp. 191
8.1.1 I/O Countsp. 191
8.1.2 Cross-Talkp. 192
8.1.3 Digital Circuitry Noisep. 193
8.2 IC Floor Planp. 193
8.2.1 Signal Flow and Substrate Couplingp. 196
8.2.2 Groundingp. 196
8.2.3 Isolationp. 197
8.3 Packaging Considerationsp. 198
8.3.1 Package Modelingp. 199
8.3.2 Bonding Limitationp. 200
8.4 Conclusionp. 200
9 Future Trendsp. 203
9.1 CMOS Cellphones
9.2 Multiband, Multimode Wireless Solutionsp. 204
9.3 60 GHz Subsystems in Silicon!p. 205
9.4 Interchip Communicationsp. 206
9.5 Ultrawideband Communication Technologyp. 210
9.6 Diversity Techniquesp. 211
9.7 Conclusionp. 213
Indexp. 217
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