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Summary
Summary
Modern telecommunication systems are highly complex from an algorithmic point of view. The complexity continues to increase due to advanced modulation schemes, multiple protocols and standards, as well as additional functionality such as personal organizers or navigation aids.
To have short and reliable design cycles, efficient verification methods and tools are necessary. Modeling and simulation need to accompany the design steps from the specification to the overall system verification in order to bridge the gaps between system specification, system simulation, and circuit level simulation. Very high carrier frequencies together with long observation periods result in extremely large computation times and requires, therefore, specialized modeling methods and simulation tools on all design levels.
The focus of Modeling and Simulation for RF System Design lies on RF specific modeling and simulation methods and the consideration of system and circuit level descriptions. It contains application-oriented training material for RF designers which combines the presentation of a mixed-signal design flow, an introduction into the powerful standardized hardware description languages VHDL-AMS and Verilog-A, and the application of commercially available simulators.
Modeling and Simulation for RF System Design is addressed to graduate students and industrial professionals who are engaged in communication system design and want to gain insight into the system structure by own simulation experiences.
The authors are experts in design, modeling and simulation of communication systems engaged at the Nokia Research Center (Bochum, Germany) and the Fraunhofer Institute for Integrated Circuits, Branch Lab Design Automation (Dresden, Germany).
Table of Contents
Preface | p. ix |
Acknowledgments | p. xi |
1 Introduction | p. 1 |
2 Design Flow Overview | p. 7 |
2.1 Design Levels | p. 7 |
2.2 Top-down System Design | p. 9 |
2.3 Bottom-up Verification | p. 11 |
3 Simulation Tools in System Design | p. 15 |
3.1 Use of Simulation Tools within the Design Flow | p. 15 |
3.2 Specific Simulation Algorithms of RF Simulators | p. 17 |
3.3 Criteria of the Simulator Selection | p. 21 |
3.4 Internet Resources for Simulation Tools | p. 23 |
4 System Level Modeling | p. 25 |
4.1 System Level Simulation | p. 25 |
4.2 Simulation Technology of System Level Simulators | p. 26 |
4.3 Complex Baseband Simulation | p. 27 |
4.3.1 Principle | p. 27 |
4.3.2 Example for baseband simulation | p. 30 |
4.3.3 Restrictions and advantages of baseband modeling | p. 30 |
4.4 Model Libraries for System Simulation | p. 31 |
4.5 Creation of Own Primitive and Hierarchical Models | p. 33 |
4.5.1 SPW modeling example | p. 33 |
5 VHDL-AMS for Block Level Simulation | p. 39 |
5.1 Introduction | p. 39 |
5.2 VHDL-AMS Standardization | p. 40 |
5.3 A Simple Block Level Example - Analog PLL | p. 41 |
5.3.1 Mathematical models of basic blocks | p. 42 |
5.3.2 Structural description of the PLL circuit in VHDL-AMS | p. 44 |
5.3.3 VHDL-AMS description of basic blocks | p. 47 |
5.4 Summary | p. 50 |
6 Introduction to VHDL-AMS | p. 51 |
6.1 Aim of this Introduction | p. 51 |
6.2 Repetition of Basics of VHDL 1076-1993 | p. 52 |
6.2.1 Design units | p. 52 |
6.2.2 Logical libraries and compilation of design units | p. 56 |
6.2.3 Concurrent statements | p. 60 |
6.2.4 A simple pure digital example - divider | p. 65 |
6.3 Conservative Systems Description | p. 66 |
6.3.1 Network analysis problem | p. 67 |
6.3.2 Nature, terminal and branch quantity declarations | p. 71 |
6.3.3 Simultaneous statements and free quantity declarations | p. 78 |
6.3.4 Example of a conservative system - A-law companding | p. 85 |
6.3.5 Attributes in VHDL-AMS | p. 88 |
6.3.6 Example - higher order lowpass filter | p. 103 |
6.4 Description of Nonconservative Systems | p. 105 |
6.5 Mixed-Signal Simulation | p. 107 |
6.5.1 Attributes for mixed-signal modeling | p. 108 |
6.5.2 Mixed-signal simulation cycle | p. 114 |
6.6 Analysis Domains | p. 116 |
6.6.1 Supported domains | p. 116 |
6.6.2 Small-signal and noise domain simulation | p. 118 |
6.7 Summary | p. 124 |
7 Selected RF Blocks in VHDL-AMS | p. 127 |
7.1 Library Overview | p. 127 |
7.2 Signal Sources | p. 128 |
7.2.1 Independent sources | p. 128 |
7.2.2 Modulated sources | p. 130 |
7.2.3 Wobble generator | p. 133 |
7.2.4 Pseudorandom binary source | p. 135 |
7.3 Basic RF Building Blocks | p. 137 |
7.3.1 Low-noise amplifier | p. 137 |
7.3.2 Mixer | p. 142 |
7.3.3 Charge pump | p. 146 |
7.3.4 Analog VCO | p. 150 |
7.3.5 Digital VCO | p. 153 |
7.3.6 Filters | p. 157 |
7.3.7 Switch | p. 163 |
7.3.8 General n-bit A/D and D/A converter | p. 164 |
7.3.9 Simple channel | p. 169 |
7.4 Measurement and Observation Units | p. 174 |
7.4.1 Peak detector | p. 174 |
7.4.2 Frequency measurement unit | p. 175 |
7.4.3 Power meter | p. 178 |
7.5 Block Level Example of a Linear PLL | p. 183 |
8 Macromodeling in VHDL-AMS | p. 191 |
8.1 Introduction | p. 191 |
8.2 General Methodology | p. 191 |
8.3 Input and Output Stages | p. 194 |
8.3.1 Input stages | p. 194 |
8.3.2 Output stages | p. 197 |
8.4 OpAmp Macromodel | p. 199 |
9 Complex Example: Wlan Receiver | p. 203 |
9.1 Introduction | p. 203 |
9.2 Example Specification | p. 204 |
9.3 Example Modeling | p. 207 |
9.4 Example Calibration | p. 211 |
9.5 Example Verification | p. 214 |
10 Modeling of Analog Blocks in Verilog-A | p. 219 |
10.1 Introduction | p. 219 |
10.2 Writing Custom Behavioral Models | p. 220 |
10.2.1 Verilog-A principles | p. 220 |
10.2.2 LNA modeling example | p. 222 |
10.2.3 Creating a Verilog-A model | p. 226 |
10.3 Overview of the Cadence Model Library rfLib | p. 231 |
10.4 Modeling and Simulation of a WLAN Receiver | p. 236 |
10.4.1 WLAN receiver modeling using Cadence libraries | p. 237 |
10.4.2 Simulation of the WLAN receiver | p. 240 |
11 Characterization for Bottom-Up Verification | p. 247 |
11.1 Concept of Characterization | p. 247 |
11.2 RF Characteristics and Parameters | p. 248 |
11.3 Application of Characterization | p. 252 |
11.4 Example Characterization of an LNA | p. 254 |
11.5 Characterization Environment | p. 258 |
11.6 Characterization Using the OCEAN Script Language | p. 262 |
11.6.1 Creation of the testbench schematic | p. 262 |
11.6.2 Analysis settings and simulation | p. 263 |
11.6.3 Combination and extension of the OCEAN scripts | p. 266 |
12 Advanced Methods for Overall System Specification and Validation | p. 271 |
12.1 Gap between System Level and Block Level Simulation | p. 271 |
12.2 File Coupling of Simulators | p. 272 |
12.3 Direct Cosimulation of System Level and Analog Simulators | p. 273 |
12.4 Generated Black Box Models | p. 279 |
References | p. 285 |
Index | p. 287 |