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Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
|---|---|---|---|---|---|
Searching... | 30000010060183 | TK5102.96 G58 2004 | Open Access Book | Book | Searching... |
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Summary
Summary
PREFACE The increasing demand on high data rate and quality of service in wireless communication has to cope with limited bandwidth and energy resources. More than 50 years ago, Shannon has paved the way to optimal usage of bandwidth and energy resources by bounding the spectral efficiency vs. signal to noise ratio trade-off. However, as any information theorist, Shannon told us what is the best we can do but not how to do it [1]. In this view, turbo codes are like a dream come true: they allow approaching the theoretical Shannon capacity limit very closely. However, for the designer who wants to implement these codes, at first sight they appear to be a nightmare. We came a huge step closer in striving the theoretical limit, but see the historical axiom repeated on a different scale: we know we can achieve excellent performance with turbo codes, but not how to realize this in real devices.
Table of Contents
| Chapter 1 Turbo Codes: Introducing the communication problem they solve, and the implementation problem they create | |
| 1.1. A communication and Microelectronics perspective | p. 1 |
| 1.1.1 Scientific fathers recalled: Shannon and Shockley | p. 1 |
| 1.1.2 Channel coding: from simple engines to turbo | p. 2 |
| 1.1.3 IC revolution: from transistors to 4G radios | p. 4 |
| 1.1.4 The implementation problem and goals | p. 5 |
| 1.2. Turbo codes: desirable channel coding solutions | p. 6 |
| 1.2.1 Channel coding: an essential ingredient in digital communication systems | p. 8 |
| 1.2.2 Block and Convolutional Channel Codes: the basics | p. 9 |
| 1.2.3 Concatenated codes | p. 15 |
| 1.2.4 Parallel concatenated convolutional (turbo) codes | p. 16 |
| 1.2.5 Decoding parallel concatenated Turbo codes | p. 18 |
| 1.2.6 Serially concatenated block codes | p. 26 |
| 1.3. Conclusions | p. 27 |
| 1.4. References | p. 28 |
| Chapter 2 Design Methodology: The Strategic Plan: Getting turbo-codes implemented at maximum performance/cost | |
| 2.1. Introduction | p. 29 |
| 2.2. Algorithmic exploration | p. 31 |
| 2.3. Data Transfer and Storage Exploration | p. 32 |
| 2.4. From architecture to silicon integration | p. 33 |
| 2.5. Conclusions | p. 36 |
| 2.6. References | p. 37 |
| Chapter 3 Conquering the Map: Removing the main bottleneck of convolutional turbo decoders | |
| 3.1. Introduction | p. 39 |
| 3.2. The MAP decoding algorithm for convolutional turbo codes | p. 40 |
| 3.3. Simplification of the MAP algorithm: log-max MAP | p. 51 |
| 3.3.1 The log-max MAP algorithm | p. 51 |
| 3.4. Trellis termination in convolutional turbo codes | p. 56 |
| 3.4.1 No termination | p. 57 |
| 3.4.2 Single termination | p. 58 |
| 3.4.3 Double termination | p. 59 |
| 3.5. MAP architecture definition: systematic approach | p. 60 |
| 3.5.1 MAP bottlenecks | p. 61 |
| 3.5.2 Data Flow and Loop Transformations | p. 61 |
| 3.5.3 Storage Cycle Budget Distribution | p. 68 |
| 3.5.4 Memory organization | p. 74 |
| 3.6. Conclusions | p. 78 |
| 3.7. References | p. 78 |
| Chapter 4 Demystifying the Fang-Buda Algorithm: Boosting the block turbo decoding | |
| 4.1. Introduction | p. 81 |
| 4.2. Soft decoding of algebraic codes | p. 83 |
| 4.2.1 Maximum likelihood decoding of block codes | p. 83 |
| 4.2.2 The Chase algorithm | p. 86 |
| 4.2.3 The Fang-Buda Algorithm (FBA) | p. 87 |
| 4.3. FBA Optimization and Architecture Derivation | p. 90 |
| 4.3.1 Data Type Refinement | p. 90 |
| 4.3.2 Data and control flow transformations | p. 91 |
| 4.3.3 Data Reuse Decision and Storage Cycle Budget Distribution | p. 93 |
| 4.3.4 Memory allocation and assignment | p. 96 |
| 4.4. FBA-based BTC decoder performance | p. 99 |
| 4.5. Conclusions | p. 103 |
| 4.6. References | p. 103 |
| Chapter 5 Mastering the Interleaver: Divide and Conquer | |
| 5.1. Introduction | p. 105 |
| 5.2. Basic elements of the interleaver | p. 107 |
| 5.3. Collision-free interleavers | p. 109 |
| 5.4. Case study: the 3GPP interleaver and a 3GPP collision-free interleaver | p. 113 |
| 5.5. Optimized scheduling for turbo decoding: collision-free interleaving and deinterleaving | p. 118 |
| 5.6. References | p. 120 |
| Chapter 6 T@MPO Codec: From theory to real life silicon | |
| 6.1. Introduction | p. 121 |
| 6.2. Positioning oneself in the optimal performance-speed-cost space | p. 122 |
| 6.3. Design flow | p. 126 |
| 6.4. Decoder final architecture | p. 128 |
| 6.5. Synthesis results | p. 131 |
| 6.6. Measurements results | p. 133 |
| 6.7. T@MPO features | p. 138 |
| 6.8. References | p. 139 |
| Abbreviations list | p. 141 |
| Symbol list | p. 145 |
| Index | p. 147 |
