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1. 
Cover image for Principles of semiconductor network testing
2. 
Cover image for Compatibility and testing of electronic components
3. 
Cover image for Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty
4. 
Cover image for An engineer's guide to automated testing of high-speed interfaces
5. 
Cover image for Design for in-situ chip testing with a compact tester
6. 
Cover image for Testability method at register transfer level (RTL) and gate level
7. 
Cover image for Testability method at register transfer level (RTL) and gate level
8. 
Cover image for Functional test generation using micro operation fault model
9. 
Cover image for Functional test generation using micro operation fault model
10. 
Cover image for Test pattern generation for path delay fault using stuck-at fault automatic test pattern generator
11. 
Cover image for ESD : failure mechanisms and models
12. 
Cover image for Nanometer technology designs : high quality delay tests