Title:
Analysis and design of digital systems with VHDL
Personal Author:
Publication Information:
Boston, MA : PWS Pub, 1997
ISBN:
9780534954109
Available:*
Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
|---|---|---|---|---|---|
Searching... | 30000003791880 | TK7868.D5 D47 1997 | Open Access Book | Book | Searching... |
On Order
Summary
Summary
Dewey presents digital engineering concepts and systems in the context of a top-down design process that moves from concept to realization using specific, step-by-step procedures. In other words, Dewey introduces and explains digital concepts and systems in the first three Parts of the book, and then demonstrates how VHDL is used to model these concepts and systems in the latter three Parts. As a result, this dual-track presentation helps readers build a critical new skill set increasingly required in industry - using a hardware description language (VHDL) to specify digital systems in formats that powerful computer-based design automation programs can process quickly, making design of complex digital systems easier and faster.
Table of Contents
| Preface |
| 1 Introduction |
| Electronic Systems |
| Digital Systems |
| Digital System Design Process |
| Design Automation |
| VHDL |
| Summary |
| 2 Representing Information |
| Representing Positive Numbers in Binary |
| Converting Between Binary and Decimal |
| Binary Arithmetic |
| Representing Negative Numbers in Binary |
| Octal and Hexadecimal Number Systems |
| Binary Codes |
| Representing Characters in Binary |
| Summary |
| Problems |
| Part I Digital Engineering: Combinational Systems |
| 3 Combinational Systems: Definition And Analysis |
| Overview of Combinational Systems |
| Switching Algebra |
| Additional Logic Operations |
| Logic Mnemonics |
| Minimal Sets of Logic Operators |
| Multi-Input Logic Operator |
| Combinational System Analysis |
| Logic Expressions |
| Documenting Combinational Systems |
| Combinational System Analysis: A Second Look |
| Summary |
| Problems |
| 4 Combinational Design: Synthesis |
| Generating Logic Expressions from Prose |
| Minimization Techniques |
| Algebraic Minimization Technique |
| Karnaugh Map Minimization Technique |
| Quine-McCluskey Minimization Technique |
| Exercise: Weather Vane |
| Summary |
| Problems |
| 5 Combinational Design: Implementation |
| Specification Versus Implementation |
| Two-Level Networks |
| Multilevel Networks |
| Multiplexers |
| Decoders |
| Memory |
| Programmable Logic Devices |
| Design Practices |
| Summary |
| Problems |
| Part II Digital Engineering: Manufacturing Technologies |
| 6 Logic Families |
| Electrical Signals and Logic Conventions |
| Metal-Oxide-Semiconductor Logic Families |
| Bipolar Logic Families |
| BiCMOS Logic Family |
| Electrical Characteristics |
| Summary |
| Problems |
| 7 Integrated Circuits |
| Diode: The pn Junction |
| Metal-Oxide-Semiconductor Transistors |
| Bipolar Transistors |
| Fabrication and Packaging |
| Application-Specific Integrated Circuits (ASICs) |
| IC Economics |
| Summary |
| Problems |
| Part III Digital Engineering: Sequential Systems |
| 8 Sequential Systems: Definition And Analysis |
| Overview of Sequential Systems |
| Memory Devices |
| Literal Analysis |
| Symbolic Analysis |
| Timing Issues |
| Summary |
| Problems |
| 9 Sequential Design: Synthesis |
| Simple Design Example |
| Generating State Diagrams from Prose |
| State Reduction |
| State Assignment and Encoded State Tables |
| Karnaugh Maps and Boolean Expressions |
| Exercise: Markov Speech Processor |
| Summary |
| Problems |
| 10 Sequential Design: Implementation |
| Combinational Logic |
| Registers |
| Shift Registers |
| Counters |
| Sequential Programmable Logic Devices (PLDs) |
| Putting It All Together |
| Summary |
| Problems |
| Part IV VHDL: Combinational Systems |
| 11 VHDL: A First look VHDL Presentation and Examples |
| Basic Language Organization |
| Interface |
| Architecture Body |
| Logic Operators |
| Concurrency |
| Design Units and Libraries |
| Summary |
| Problems |
| 12 Structural Modeling In VHDL: Part I Example Schematic |
| Component and Signal Declarations |
| Component Instantiation Statements |
| Hierarchical Structures |
| Packages |
| Name Spaces and Scope |
| VHDL-93: Direct Design Entity Instantiation |
| Summary |
| Problems |
| 13 Data Flow Modeling In VHDL Modeling Styles |
| Conditional Concurrent Signal Assignment Statement |
| Relational Operators |
| Selected Concurrent Signal Assignment Statement |
| Data Flow and Hardware Parallelism |
| Alternative Operators |
| Summary |
| Problems |
| 14 Structural Modeling In VHDL: Part II Port Modes and Their Proper use |
| Constant-Valued and Unconnected Ports |
| Regular Structures |
| Generate Statements |
| Unconstrained Ports |
| Generics and Parameterized Design Entities |
| Arithmetic Operators |
| Integer and Floating Points Literals |
| VHDL-93: Foreign Architectures |
| VHDL-93: New Structure Attribute |
| Summary |
| Problems |
| Part V Manufacturing Technologies |
| 15 VHDL Technology Information: Part I Specifying Physical Values |
| Propagation Delay |
| Functions |
| VHDL-93: Pure and Impure Functions |
| Modeling Wired Logic |
| Prohibiting Wired Logic |
| Signals, Variables, and Constants |
| Summary |
| Problems |
| 16 VHDL Technology Information: Part II Multi-Valued Logic |
| Enumeration Types |
| Arrays |
| VHDL-93: Bit String Literals |
| User-Defined At |
