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Cover image for Digital design of IEEE single precision floating point divider using VHDL implement in FPGA
Title:
Digital design of IEEE single precision floating point divider using VHDL implement in FPGA
Personal Author:
Koh, Kai Ngiap
Publication Information:
Skudai : Universiti Teknologi Malaysia, 2003
Subject Term:
Floating-point arithmetic

VHDL (Computer hardware description language)
DSP_DISSERTATION:
Project Paper (Bachelor of Electrical Engineering (Electronics)) - Universiti Teknologi Malaysia, 2003

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 30000010026686 QA76.6 K63 2003 Closed Access Thesis UTM Project Paper (Closed Access)
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