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Cover image for Design through Verilog HDL
Title:
Design through Verilog HDL
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Publication Information:
Hoboken, N.J. : Wiley-Interscience, 2004
ISBN:
9780471441489

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30000010070330 TK7885.7 P32 2004 Open Access Book Book
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Summary

Summary

A comprehensive resource on Verilog HDL for beginners and experts

Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.

Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant.

Other important topics covered include:

Primitives Gate and Net delays Buffers CMOS switches State machine design Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design.

Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource.


Author Notes

B. Bala Tripura Sundari is a Senior Lecturer in the ECE Department of the Amrita Institute of Technology.


Reviews 1

Choice Review

Padmanabhan and Sundari (both, Amrita Institute of Technology, India) offer a book ideally suited for teaching digital hardware design techniques using a low-level programming language. They clearly demonstrate how Verilog HDL (hardware description language) allows one to create electronic circuit designs at various levels of abstraction (architectural, behavioral, gate and switch) and the subsequent stages in the design process of very large scale integration (VLSI) integrated circuit layouts. Topics include the syntax and semantics of Verilog HDL, gate and switch level logic simulation, system functionality modeling, and programmable logic devices. These topics are thoroughly and robustly presented with the help of a multitude of examples and diagrams. The authors consistently display the rare ability to simplify complex design topics, making the book a delight for those with minimal programming and digital logic experience, although a quick refresher in digital logic and a few pages devoted to the primitives of Boolean algebra would be appropriate. Nonetheless, it accurately describes the digital hardware design process. ^BSumming Up: Highly recommended. Upper-division undergraduates through professionals. M. Connell SUNY College at Cortland


Table of Contents

Prefacep. xi
Acknowledgementsp. xiii
1 Introduction to Vlsi Designp. 1
1.1 Introductionp. 1
1.2 Conventional Approach to Digital Designp. 1
1.3 Vlsi Designp. 3
1.4 Asic Design Flowp. 4
1.5 Role of Hdlp. 9
2 Introduction to Verilogp. 11
2.1 Verilog as an Hdlp. 11
2.2 Levels of Design Descriptionp. 11
2.3 Concurrencyp. 13
2.4 Simulation and Synthesisp. 14
2.5 Functional Verificationp. 14
2.6 System Tasksp. 16
2.7 Programming Language Interface (PLI)p. 16
2.8 Modulep. 16
2.9 Simulation and Synthesis Toolsp. 22
2.10 Test Benchesp. 27
3 Language Constructs and Conventions in Verilogp. 31
3.1 Introductionp. 31
3.2 Keywordsp. 31
3.3 Identifiersp. 32
3.4 White Space Charactersp. 33
3.5 Commentsp. 33
3.6 Numbersp. 34
3.7 Stringsp. 36
3.8 Logic Valuesp. 38
3.9 Strengthsp. 39
3.10 Data Typesp. 40
3.11 Scalars and Vectorsp. 41
3.12 Parametersp. 42
3.13 Memoryp. 43
3.14 Operatorsp. 43
3.15 System Tasksp. 44
3.16 Exercisesp. 46
4 Gate Level Modeling-1p. 47
4.1 Introductionp. 47
4.2 And Gate Primitivep. 47
4.3 Module Structurep. 50
4.4 Other Gate Primitivesp. 51
4.5 Illustrative Examplesp. 51
4.6 Tri-State Gatesp. 64
4.7 Array of Instances of Primitivesp. 66
4.8 Additional Examplesp. 69
4.9 Exercisesp. 79
5 Gate Level Modeling-2p. 81
5.1 Introductionp. 81
5.2 Design of Flip-Flops with Gate Primitivesp. 81
5.3 Delaysp. 91
5.4 Strengths and Contention Resolutionp. 102
5.5 Net Typesp. 109
5.6 Design of Basic Circuitsp. 115
5.7 Exercisesp. 124
6 Modeling at Data Flow Levelp. 127
6.1 Introductionp. 127
6.2 Continuous Assignment Structuresp. 127
6.3 Delays and Continuous Assignmentsp. 133
6.4 Assignment to vectorsp. 135
6.5 Operatorsp. 136
6.6 Additional Examplesp. 150
6.7 Exercisesp. 157
7 Behavioral Modelingp. 159
7.1 Introductionp. 159
7.2 Operations and Assignmentsp. 160
7.3 Functional Bifurcationp. 161
7.4 Initial Constructp. 164
7.5 Always Constructp. 168
7.6 Examplesp. 170
7.7 Assignments with Delaysp. 184
7.8 Wait Constructp. 192
7.9 Multiple Always Blocksp. 195
7.10 Designs at Behavioral Levelp. 197
7.11 Blocking and Nonblocking Assignmentsp. 201
7.12 The case Statementp. 205
7.13 Simulation Flowp. 214
7.14 Exercisesp. 217
8 Behavioral Modeling IIp. 219
8.1 Introductionp. 219
8.2 If and if-else Constructsp. 219
8.3 Assign-deassign Constructp. 225
8.4 Repeat Constructp. 236
8.5 For Loopp. 238
8.6 The disable Constructp. 244
8.7 While Loopp. 249
8.8 Forever Loopp. 254
8.9 Parallel Blocksp. 258
8.10 Force-release Constructp. 261
8.11 Eventp. 266
8.12 Exercisesp. 268
9 Functions, Tasks, and User-Defined Primitivesp. 273
9.1 Introductiuonp. 273
9.2 Functionp. 273
9.3 Tasksp. 286
9.4 User-Defined Primitives (UDP)p. 292
9.5 Exercisesp. 302
10 Switch Level Modelingp. 305
10.1 Introductionp. 305
10.2 Basic Transistor Switchesp. 305
10.3 Cmos Switchp. 318
10.4 Bidirectional Gatesp. 328
10.5 Time Delays with Switch Primitivesp. 333
10.6 Instantiations with Strengths and Delaysp. 334
10.7 Strength Contention with Trireg Netsp. 334
10.8 Exercisesp. 337
11 System Tasks, Functions, and Compiler Directivesp. 339
11.1 Introductionp. 339
11.2 Parametersp. 339
11.3 Path Delaysp. 348
11.4 Module Parametersp. 371
11.5 System Tasks and Functionsp. 373
11.6 File-Based Tasks and Functionsp. 383
11.7 Compiler Directivesp. 385
11.8 Hierarchical Accessp. 393
11.9 General Observationsp. 404
11.10 Exercisesp. 405
12 Queues, Plas, and Fsmsp. 407
12.1 Introductionp. 407
12.2 Queuesp. 407
12.3 Programmable Logic Devices (PLDs)p. 414
12.4 Design of Finite State Machinesp. 418
12.5 Exercisesp. 433
Appendix A Keywords and Their Significancep. 443
Appendix B Truth Tables of Gates and Switchesp. 447
Referencesp. 449
Indexp. 451
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