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Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
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Searching... | 30000010178270 | TK7874.75 V47 2006 | Open Access Book | Book | Searching... |
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Summary
Summary
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
Author Notes
Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).
Kwang-Ting (Tim) Cheng, Ph.D., is a Professor and Chair of the Electrical and Computer Engineering Department at the University of California, Berkeley. A Fellow of the IEEE, he has published over 300 technical papers, co-authored three books, and holds 11 U.S. Patents.
Table of Contents
Chapter 1 Introduction |
Chapter 2 Design for Testability |
Chapter 3 Logic and Fault Simulation |
Chapter 4 Test Generation |
Chapter 5 Logic Built-In Self-Test |
Chapter 6 Test Compression |
Chapter 7 Logic Diagnosis |
Chapter 8 Memory Testing and Built-In Self-Test |
Chapter 9 Memory Diagnosis and Built-In Self-Repair |
Chapter 10 Boundary Scan and Core-Based Testing |
Chapter 11 Analog and Mixed-Signal Testing |
Chapter 12 Test Technology Trends in the Nanometer Age |