Title:
Iterative RLC models for interconnect delay optimization in VLSI ruting algorithms
Series:
Siri kertas kerja penyelidikan (Universiti Teknologi Malaysia. Pusat Pengurusan Penyelidikan)
Publication Information:
Skudai : Universiti Teknologi Malaysia, 2008
Added Conference Author:
Available:*
Library | Item Barcode | Material Type | Item Category 1 | Status |
---|---|---|---|---|
Searching... | 30000010207980 | Book | Book | Searching... |