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Cover image for Iterative RLC models for interconnect delay optimization in VLSI ruting algorithms
Title:
Iterative RLC models for interconnect delay optimization in VLSI ruting algorithms
Series:
Siri kertas kerja penyelidikan (Universiti Teknologi Malaysia. Pusat Pengurusan Penyelidikan)
Publication Information:
Skudai : Universiti Teknologi Malaysia, 2008

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