Defect-oriented testing for nano-metric CMOS VLSI circuits

Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.

Dedication	p. v
Preface	p. xiii
Foreword	p. xvii
Foreword for the First Edition	p. xix
Acknowledgements	p. xxi
Chapter 1 Introduction	p. 1
1 Evolution of CMOS Technology	p. 1
2 The Test Complexity	p. 5
3 Quality and Reliability Awareness	p. 9
4 Building Quality and Reliability	p. 11
5 Objectives of this Book	p. 15
6 Book Organization	p. 16
Chapter 2 Functional and Parametric Defect Models	p. 23
1 Brief Classification of Defects	p. 23
1.1 Defect-Fault Relationship	p. 26
2 Induetieve Fault Analysis	p. 28
2.1 IC Design and Layout Related Defect Sensitivity	p. 29
2.2 Defect Sensitive Design	p. 29
2.3 Basic Concepts of IFA	p. 30
3 Parametric Defect and Fault Models	p. 32
3.1 Threshold Voltage Mismatch ([Delta]V[subscript t]) Fault Modeling	p. 32
3.2 Sources of Threshold Voltage Variability	p. 33
3.3 Leakage Current due to V[subscript t] Mismatch	p. 34
3.4 Delay in Parallel-connected Networks	p. 39
3.5 Delay Variation Model with [Delta]V[subscript t] for Parallel Transistor Networks	p. 41
3.6 Spot Defect Statistics: Resistive Opens	p. 45
4 Functional Defect Models	p. 50
4.1 Critical Areas	p. 53
4.2 Defect Statistics	p. 54
4.3 Average Probability of Failure of Long Interconnects	p. 58
4.4 Average Critical Area of N Conductors	p. 61
5 Conclusions	p. 64
Chapter 3 Digital CMOS Fault Modeling	p. 69
1 Objectives of Fault Modeling	p. 69
2 Levels of Testing	p. 71
3 Levels of Fault Modeling	p. 73
3.1 Logic Level Fault Modeling	p. 73
3.2 Transistor Level Fault Modeling	p. 81
3.3 Layout Level Fault Modeling	p. 90
3.4 Function Level Fault Modeling	p. 91
3.5 Delay Fault Models	p. 92
3.6 Leakage Fault Model	p. 97
3.7 Temporary Faults	p. 98
4 Conclusions	p. 102
Chapter 4 Defects in Logic Circuits and their Test Implications	p. 111
1 Introduction	p. 111
2 Stuck-at Faults and Manufacturing Defects	p. 113
2.1 Study by Galiay, Crouzet and Vergniault	p. 114
2.2 Study by Banerjee and Abraham	p. 115
2.3 Study by Maly, Ferguson and Shen	p. 120
2.4 Gate Oxide Shorts: Study by Hawkins and Soden	p. 123
3 IFA Experiments on Standard Cells	p. 126
4 I[subscript DDQ] versus Voltage Testing	p. 130
5 Defects in Sequential Circuits	p. 133
5.1 Undetected Defects	p. 135
5.2 Defect Detection Technique	p. 137
5.3 I[subscript DDQ] Testable Flip-flop	p. 139
5.4 Defects and Scan Chains	p. 139
6 Defect Classes and their Testing	p. 143
7 Application of IFA in Nano-metric Technologies	p. 143
8 Conclusions	p. 146
Chapter 5 Testing Defects and Parametric Variations in RAMs	p. 151
1 Introduction	p. 151
2 Traditional RAM Fault Models	p. 153
2.1 Stuck-at Fault Model	p. 153
2.2 Coupling Fault Model	p. 154
2.3 Pattern Sensitivity Fault Model	p. 154
3 Defect Based RAM Fault Model Development	p. 155
3.1 Defect based SRAM Fault Models and Test Algorithms	p. 155
3.2 Subsequent Defect-oriented SRAM Test Development	p. 160
3.3 Defect based DRAM Fault Models and Test Algorithms	p. 163
3.4 TCAM Fault Models and Test Algorithms	p. 176
4 Address Decoder Defects	p. 185
4.1 Early Work on Address Decoder Faults	p. 187
4.2 Technological Differences	p. 187
4.3 Failure and Analysis	p. 189
4.4 Why Non-detection by March Tests?	p. 192
4.5 Address Decoder Open Defects	p. 193
4.6 Supplementary Test Algorithm	p. 195
4.7 Testability Techniques for Decoder Open Defects	p. 197
4.8 Recent Work on Address Decoder Defects	p. 200
5 Parametric Testing of SRAMs	p. 200
5.1 SRAM Cell and SNM	p. 203
5.2 Process Variation and SNM	p. 207
5.3 Manufacturing Defects and SNM	p. 209
5.4 Weak Cell Fault Model	p. 210
5.5 DfT Techniques to Detect Weak Cells	p. 211
6 I[subscript DDQ] Based RAM Testing	p. 215
7 Conclusions	p. 215
Chapter 6 Defect-oriented Analog Testing	p. 225
1 Introduction	p. 226
2 Analog Test Complexity	p. 227
3 Previous Work	p. 228
3.1 Estimation Method	p. 228
3.2 Topological Method	p. 228
3.3 Taxonomical Method	p. 230
4 Defect Based Realistic Fault Dictionary	p. 230
4.1 Implementation	p. 234
5 A Case Study	p. 240
5.1 Fault Matrix Generation	p. 240
5.2 Stimuli Matrix	p. 242
5.3 Simulation Results	p. 243
5.4 Silicon Results	p. 244
5.5 Observations and Analysis	p. 248
5.6 IFA: Strengths and Weaknesses	p. 249
6 Input Stimuli Generation	p. 251
6.1 Power Supply Ramp Input Test Stimuli	p. 252
6.2 Amplifier Specs	p. 254
6.3 Structural vs. Functional Fault Coverage	p. 259
6.4 Experimental Results	p. 264
7 IFA Based Fault Grading and DfT for Analog Circuits	p. 268
7.1 A/D Converter Testing	p. 268
7.2 Description of the Experiment	p. 269
7.3 Fault Simulation Issues	p. 270
7.4 Fault Simulation Results	p. 272
8 High Level Analog Fault Models	p. 278
9 Conclusions	p. 281
Chapter 7 Yield Engineering	p. 289
1 Mathematical Models for Yield Prediction	p. 289
1.1 Layout Oriented Yield Prediction	p. 300
2 Yield Engineering	p. 301
3 Economics and Yield Forecasting	p. 306
4 Conclusions	p. 312
Chapter 8 Conclusion	p. 317
1 Test and Yield Engineering Complexity in Nano-metric Technologies	p. 317
2 Role of Defect-oriented Testing	p. 320
2.1 Strengths of Defect-oriented Testing	p. 320
2.2 Limitations of Defect-oriented Testing	p. 321
3 Future Directions	p. 321
Index	p. 325

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